Floating point multiplier with reduced critical paths using delay matching techniques
AssigneeSun Microsystems, Inc.
InventorsRobert K. Yu, Gregory B. Zyner
Life of this patent
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Abstract
A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53.times.53 double-precision product. Delay matching techniques in the binary tree stage and in the final addition stage reduce cycle time. Improved rounding and sticky-bit generating techniques further reduce area and timing. The overall multiplier has a latency of 3 cycles, a throughput of 1 cycle, and a cycle time of 6.0 ns.
Claims24
An apparatus including an integrated, double-precision floating point multiplier circuit, said multiplier circuit comprising:
- a plurality of input signal terminals;
- a plurality of output signal terminals;
- and
- a binary tree adder array, coupled to said pluralities of input and output signal terminals, for receiving a plurality of multiplier data and a plurality of multiplicand data via said plurality of input signal terminals and in response thereto providing a plurality of product data via said plurality of output signal terminals;
- wherein said binary tree adder array includes a plurality of rows of adders which are interleaved, is integrated in a regular structure with a plurality of edges and is justified along a first one of said plurality of edges, and wherein said pluralities of input and output signal terminals are located along a second one of said plurality of edges, and further wherein selected ones of said plurality of rows of adders contain one or more adders which are associated with other ones of said plurality of rows of adders such that said selected ones and said other ones of said plurality of rows of adders contain approximately equal numbers of adders.
A method of providing an apparatus including an integrated, double-precision floating point multiplier circuit, said method comprising the steps of:
- providing a plurality of input signal terminals;
- providing a plurality of output signal terminals;
- and
- providing a binary tree adder array, coupled to said pluralities of input and output signal terminals, for receiving a plurality of multiplier data and a plurality of multiplicand data via said plurality of input signal terminals and in response thereto providing a plurality of product data via said plurality of output signal terminals;
- wherein said binary tree adder array includes a plurality of rows of adders which are interleaved, is integrated in a regular structure with a plurality of edges and is justified along a first one of said plurality of edges, and wherein said pluralities of input and output signal terminals are located along a second one of said plurality of edges, and further wherein selected ones of said plurality of rows of adders contain one or more adders which are associated with other ones of said plurality of rows of adders such that said selected ones and said other ones of said plurality of rows of adders contain approximately equal numbers of adders.
A method of performing double-precision floating point multiplication within an integrated structure, said method comprising the steps of:
- receiving a plurality of multiplier data and a plurality of multiplicand data via a plurality of input signal terminals;
- and
- providing, via a plurality of output signal terminals, a plurality of product data with a binary tree adder array in response to said pluralities of multiplier and multiplicand data;
- wherein said binary tree adder array includes a plurality of rows of adders which are interleaved, is integrated in a regular structure with a plurality of edges and is justified along a first one of said plurality of edges, and wherein said pluralities of input and output signal terminals are located along a second one of said plurality of edges, and further wherein selected ones of said plurality of rows of adders contain one or more adders which are associated with other ones of said plurality of rows of adders such that said selected ones and said other ones of said plurality of rows of adders contain approximately equal numbers of adders.
Dependencies are inferred from the claim text.