Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals

In a digital TV receiver including a source of two's complement binary signals and circuitry for processing said binary signals, which circuitry tends to increase the number of bit positions of the processed signal to M bit positions, apparatus for symmetrically truncating said M-bit binary signals to (M-N) bits where M and N are integers, said apparatus comprising:

• an input port for applying said M-bit binary signals;
• means coupled to said input port, and responsive to the N LSB's of said M-bit binary signal and the MSB of said M-bit binary signal for producing a control signal whenever at least one of said N LSB's of the M-bit binary signal and the MSB of said M-bit binary signal are concurrently in a logical one state;
• means coupled to said input port, and responsive to said control signal for incrementing by one unit the (M-N) MSB's of said M-bit binary signal and providing the incremented (M-N) MSB's as a truncated (M-N)-bit binary signal, and in the absence of said control signal providing the (M-N) MSB's of said M-bit binary signal as a truncated (M-N)-bit binary signal.

In a digital TV receiver including a source of two's complement binary signal corresponding to composite video signal and digital circuitry for processing a chrominance component of said composite binary signals, which circuitry tends to increase the number of bit positions of the processed binary signal to M bit positions, apparatus for symmetrically truncating said M-bit binary signals to (M-N) bits, where M an N are integers, said apparatus comprising:

• an input port for applying said M-bit binary signals;
• means coupled to said input port, and responsive to the N LSB's of said M-bit binary signal and the MSB of said M-bit binary signal for producing a control signal whenever at least one of said N LSB's of the M-bit binary signal and the MSB of said M-bit binary signal are concurrently in a logical one state;
• means coupled to said input port, and responsive to said control signal for incrementing by one unit the (M-N) MSB's of said M-bit binary signal and providing the incremented (M-N) MSB's as a truncated (M-N)-bit binary signal, and in the absence of said control signal providing the (M-N) MSB's of said M-bit binary signal as a truncated (M-N)-bit binary signal.

The method of truncating M-bit two's complement binary signals to (M-N)-bit two's complement signals, where M and N are integers, comprising:

• discarding the N LSB's of said binary signals and outputting the (M-N) MSB's of said binary signals for all positive values of signals and for negative values of signals that do not contain logical ones in their N LSB positions;
• and
• discarding the N LSB's of said binary signals and algebraically adding a positive one unit to the (M-N) MSB's of said binary signals and outputting the incremented (M-N) MSB's of said binary signals for negative values of signals whenever any one of the N LSB's of said negative values is a logical one.