Method and apparatus for performing high-precision multiply-add calculations using independent multiply and add instruments

A floating point arithmetic unit for performing independent multiply and add operations in the execution of a multiply-add instruction on three operands A, B, and C, wherein A being the multiplicand, C being the multiplier and B being the addend, and each operand comprising data of a prescribed number p of bits in accordance with a given floating-point precision including one (1) sign bit indicating if a data represents a positive (+) or a negative (-) value, x exponent bits, and y mantissa bits, said arithmetic unit comprising:

• (a) a multiplier unit including an input stage for receiving operands A and C and having an external datapath width of d bits, wherein p<d.ltoreq.2p, and further wherein the input stage includes a respective buffer of b bits of zeros (0's) concatenated to the right of a respective least significant bit of each of operands A and C, wherein b is equal to d-p bits, said multiplier unit further including an output stage for conveying a product A*C including d upper order bits AC.sub.UPPER and d lower order bits AC.sub.LOWER ;
• (b) a sticky collect unit for receiving AC.sub.LOWER and generating a sticky bit representative of a logical OR of all of the bits of AC.sub.LOWER, wherein the sticky bit equals one (1) upon any of the bits of AC.sub.LOWER being one (1);
• (c) an adder unit having an input stage for receiving AC.sub.UPPER and operand B and having an external datapath width of d bits, and further wherein the input stage includes a buffer of b bits of zeros (0's) concatenated to the right of a least significant bit of operand B, wherein b is equal to d minus p bits, said adder unit further including an output stage for providing a resultant quantity +/- AC.sub.UPPER +/- B, wherein said multiplier unit, said sticky collect unit, and said adder unit implement an integrated multiply-add sequence;
• (d) means for rounding the resultant quantity +/- AC.sub.UPPER +/- B to a precision of bits in response to the sticky bit and further in accordance to a desired rounding mode, said rounding means further providing a multiply-add output of said arithmetic unit;
• (e) means for detecting an occurrence of either a first risk condition or a second risk condition in connection with the resultant quantity prior to a rounding of the resultant quantity by said rounding means, the first risk condition indicative of an undesirable cancellation on the resultant quantity +/- AC.sub.UPPER +/- B and the second risk condition indicative of a specific loss of precision in the resultant quantity +/- AC.sub.UPPER +/- B, said risk condition detection means further for triggering a trap upon a detection of a risk condition, the trap for discarding the resultant quantity +/- AC.sub.UPPER +/- B and further for initiating an extended multiply-add sequence;
• and
• (f) means for implementing the extended multiply-add sequence upon the three operands A, B, and C in response to the trap and providing a multiply-add output of said arithmetic unit, wherein the extended multiply-add sequence is selected for achieving mathematical compatibility with the integrated multiply-add sequence, wherein said multiplier unit includes an internal datapath width of 2d bits and said adder unit includes an internal datapath width of d+1 bits, further wherein said multiplier unit and said adder unit are interconnected by an external communication link of d bits and capable of producing resultant quantities having a precision of p.ltoreq.d.

A floating point arithmetic unit for performing independent multiply and add operations in the execution of a multiply-add instruction on three operands A, B, and C, wherein A being the multiplicand, C being the multiplier and B being the addend, and each operand comprising data of a prescribed number p of bits in accordance with a given floating-point precision including one (1) sign bit indicating if a data represents a positive (+) or a negative (-) value, x exponent bits, and y mantissa bits, said arithmetic unit comprising:

• (a) a multiplier unit including an input stage for receiving operands A and C and having an external datapath width of d bits, wherein p<d.ltoreq.2p, and further wherein the input stage includes a respective buffer of b bits of zeros (0's) concatenated to the right of a respective least significant bit of each of operands A and C, wherein b is equal to d-p bits, said multiplier unit further including an output stage for conveying a product A*C including d upper order bits AC.sub.UPPER and d lower order bits AC.sub.LOWER ;
• (b) a sticky collect unit for receiving AC.sub.LOWER and generating a sticky bit representative of a logical OR of all of the bits of AC.sub.LOWER, wherein the sticky bit equals one (1) upon any of the bits of AC.sub.LOWER being one (1);
• (c) an adder unit having an input stage for receiving AC.sub.UPPER and operand B and having an external datapath width of d bits, and further wherein the input stage includes a buffer of b bits of zeros (0's) concatenated to the right of a least significant bit of operand B, wherein b is equal to d minus p bits, said adder unit further including an output stage for providing a resultant quantity +/- AC.sub.UPPER +/- B, wherein said multiplier unit, said sticky collect unit, and said adder unit implement an integrated multiply-add sequence;
• (d) means for rounding the resultant quantity +/- AC.sub.UPPER +/- B to a precision of p bits in response to the sticky bit and further in accordance to a desired rounding mode, said rounding means further providing a multiply-add output of said arithmetic unit;
• (e) means for detecting an occurrence of either a first risk condition or a second risk condition in connection with the resultant quantity prior to a rounding of the resultant quantity by said rounding means, the first risk condition indicative of an undesirable cancellation on the resultant quantity +/- AC.sub.UPPER +/- B and the second risk condition indicative of a specific loss of precision in the resultant quantity +/- AC.sub.UPPER +/- B, said risk condition detection means further for triggering a trap upon a detection of a risk condition, the trap for discarding the resultant quantity +/- AC.sub.UPPER +/- B and further for initiating an extended multiply-add sequence;
• and
• (f) means for implementing the extended multiply-add sequence upon the three operands A, B, and C in response to the trap and providing a multiply-add output of said arithmetic unit, wherein the extended multiply-add sequence is selected for achieving mathematical compatibility with the integrated multiply-add sequence, wherein said multiplier unit and said adder unit each further includes an 81-bit internal communication link including one (1) sign bit, sixteen (16) exponent bits, and sixty-four (64) mantissa bits.

A floating point arithmetic method for performing independent multiply and add operations in the execution of a multiply-add instruction on three operands A, B, and C, wherein A being the multiplicand, C being the multilplier and B being the addend, and each operand comprising data of a prescribed number p of bits in accordance with a given floating-point precision including one (1) sign bit indicating if a data represents a positive (+) or a negative (-) value, x exponent bits, and y mantissa bits, said method comprising the steps of:

• (a) providing a multiplier unit including an input stage for receiving operands A and C and having an external datapath width of d bits, wherein p<d.ltoreq.2p, and further wherein the input stage includes a respective buffer of b bits of zeros (0's) concatenated to the right of a respective least significant bit of each of operands A and C, wherein b is equal to d-p bits, said multiplier unit further including an output stage for conveying a product A*C including d upper order bits AC.sub.UPPER and d lower order bits AC.sub.LOWER ;
• (b) providing a sticky collect unit for receiving AC.sub.LOWER and generating a sticky bit representative of a logical OR of all of the bits of AC.sub.LOWER, wherein the sticky bit equals one (1) upon any of the bits of AC.sub.LOWER being one (1);
• (c) providing an adder unit having an input stage for receiving AC.sub.UPPER and operand B and having an external datapath of d bits, and further wherein the input stage includes a buffer of b bits of zeros (0's) concatenated to the right of a least significant bit of operand B, wherein b is equal to d minus p bits, said adder unit further including an output stage for providing a resultant quantity +/- AC.sub.UPPER +/- B, wherein the multiplier unit, the sticky collect unit, and the adder unit implement an integrated multiply-add sequence;
• (d) rounding the resultant quantity +/- AC.sub.UPPER +/- B to a precision of p bits in response to the sticky bit and further in accordance to a desired rounding mode, said rounding step further providing a multiply-add output;
• (e) detecting an occurrence of either a first risk condition or a second risk condition in connection with the resultant quantity prior to a rounding of the resultant quantity by said rounding step, the first risk condition indicative of an undesirable cancellation on the resultant quantity +/- AC.sub.UPPER +/- B and the second risk condition indicative of a specific loss of precision in the resultant quantity +/- AC.sub.UPPER +/- B, said risk condition detection step further triggering a trap upon a detection of a risk condition, the trap for discarding the resultant quantity +/- AC.sub.UPPER +/- B and further for initiating extended multiply-add sequence;
• and
• (f) implementing the extended multiply-add sequence upon the three operands A, B, and C in response to the trap and providing a multiply-add output, wherein the extended multiply-add sequence is selected for achieving mathematical compatibility with the integrated multiply-add sequence, wherein said extended multiply-add sequence implementation step includes
• providing a multiplier means having a narrowed datapath width of p bits for receiving operands A and C and performing a first and a second multiply for providing an intermediate product A*C including a partial product of p upper order bits AC.sub.(2p-1:p) and a partial product of p lower order bits AC.sub.(p-1:0) ;
• executing three passes through an adder unit in accordance with the following operation:
• AC+B=(AC.sub.(2p-1:p) +B/2)+(AC.sub.(p-1:0) +B/2,
• and providing an intermediate resultant quantity AC+B of infinite precision;
• and
• rounding the intermediate resultant quantity AC+B to a precision of p bits and providing an output corresponding to the multiply-add output.

A floating point arithmetic method for performing independent multiply and add operations in the execution of a multiply-add instruction on three operands A, B, and C, wherein A being the multiplicand, C being the multiplier and B being the addend, and each operand comprising data of a prescribed number p of bits in accordance with a given floating-point precision including one (1) sign bit indicating if a data represents a positive (+) or a negative (-) value, x exponent bits, and y mantissa bits, said method comprising the steps of:

• (a) providing a multiplier unit including an input stage for receiving operands A and C and having an external datapath width of d bits, wherein p<d.ltoreq.2p, and further wherein the input stage includes a respective buffer of b bits of zeros (0's) concatenated to the right of a respective least significant bit of each of operands A and C, wherein b is equal to d-p bits, said multiplier unit further including an output stage for conveying a product A*C including d upper order bits AC.sub.UPPER and d lower order bits AC.sub.LOWER ;
• (b) providing a sticky collect unit for receiving AC.sub.LOWER and generating a sticky bit representative of a logical OR of all of the bits of AC.sub.LOWER, wherein the sticky bit equals one (1) upon any of the bits of AC.sub.LOWER being one (1);
• (c) providing an adder unit having an input stage for receiving AC.sub.UPPER and operand B and having an external datapath of d bits, and further wherein the input stage includes a buffer of b bits of zeros (0's) concatenated to the right of a least significant bit of operand B, wherein b is equal to d minus p bits, said adder unit further including an output stage for providing a resultant quantity +/- AC.sub.UPPER +/- B, wherein the multiplier unit, the sticky collect unit, and the adder unit implement an integrated multiply-add sequence;
• (d) rounding the resultant quantity +/- AC.sub.UPPER +/- B to a precision of p bits in response to the sticky bit and further in accordance to a desired rounding mode, said rounding step further providing a multiply-add output;
• (e) detecting an occurrence of either a first risk condition or a second risk condition in connection with the resultant quantity prior to a rounding of the resultant quantity by said rounding step, the first risk condition indicative of an undesirable cancellation on the resultant quantity +/- AC.sub.UPPER +/- B and the second risk condition indicative of a specific loss of precision in the resultant quantity +/- AC.sub.UPPER +/- B, said risk condition detection step further triggering a trap upon a detection of a risk condition, the trap for discarding the resultant quantity +/- AC.sub.UPPER +/- B and further for initiating an extended multiply-add sequence;
• and
• (f) implementing the extended multiply-add sequence upon the three operands A, B, and C in response to the trap and providing a multiply-add output, wherein the extended multiply-add sequence is selected for achieving mathematical compatibility with the integrated multiply-add sequence, wherein the multiplier unit includes an internal datapath width of 2d bits and the adder unit includes an internal datapath width of d+1 bits, further wherein the multiplier unit and the adder unit are interconnected by an external communication link of d bits and capable of producing resultant quantities having a precision of p.ltoreq.d.

A floating point arithmetic method for performing independent multiply and add operations in the execution of a multiply-add instruction on three operands A, B, and C, wherein A being the multiplicand, C being the multiplier and B being the addend, and each operand comprising data of a prescribed number p of bits in accordance with a given floating-point precision including one (1) sign bit indicating if a data represents a positive (+) or a negative (-) value, x exponent bits, and y mantissa bits, said method comprising the steps of:

• (a) providing a multiplier unit including an input stage for receiving operands A and C and having an external datapath width of d bits, wherein p<d.ltoreq.2p, and further wherein the input stage includes a respective buffer of b bits of zeros (0's) concatenated to the right of a respective least significant bit of each of operands A and C, wherein b is equal to d-p bits, said multiplier unit further including an output stage for conveying a product A*C including d upper order bits AC.sub.UPPER and d lower order bits AC.sub.LOWER ;
• (b) providing a sticky collect unit for receiving AC.sub.LOWER and generating a sticky bit representative of a logical OR of all of the bits of AC.sub.LOWER, wherein the sticky bit equals one (1) upon any of the bits of AC.sub.LOWER being one (1);
• (c) providing an adder unit having an input stage for receiving AC.sub.UPPER and operand B and having an external datapath of d bits, and further wherein the input stage includes a buffer of b bits of zeros (0's) concatenated to the right of a least significant bit of operand B, wherein b is equal to d minus p bits, said adder unit further including an output stage for providing a resultant quantity +/- AC.sub.UPPER +/- B, wherein the multiplier unit, the sticky collect unit, and the adder unit implement an integrated multiply-add sequence;
• (d) rounding the resultant quantity +/- AC.sub.UPPER +/- B to a precision of p bits in response to the sticky bit and further in accordance to a desired rounding mode, said rounding step further providing a multiply-add output;
• (e) detecting an occurrence of either a first risk condition or a second risk condition in connection with the resultant quantity prior to a rounding of the resultant quantity by said rounding step, the first risk condition indicative of an undesirable cancellation on the resultant quantity +/- AC.sub.UPPER +/- B and the second risk condition indicative of a specific loss of precision in the resultant quantity +/- AC.sub.UPPER +/- B, said risk condition detection step further triggering a trap upon a detection of a risk condition, the trap for discarding the resultant quantity +/- AC.sub.UPPER +/- B and further for initiating an extended multiply-add sequence;
• and
• (f) implementing the extended multiply-add sequence upon the three operands A, B, and C in response to the trap and providing a multiply-add output, wherein the extended multiply-add sequence is selected for achieving mathematical compatibility with the integrated multiply-add sequence wherein the multiplier unit and the adder unit each further includes an 81-bit internal communication link including one (1) sign bit, sixteen (16) exponent bits, and sixty-four (64) mantissa bits.