US 10,078,512 B2Granted

Processing denormal numbers in FMA hardware

AssigneeVia Alliance Semiconductor Co., Ltd.

InventorThomas Elmer

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Abstract

A microprocessor includes FMA execution logic that determines whether to accumulate an accumulator operand C to the partial products of multiplier and multiplicand operands A and B in the partial product adder or in a second accumulation stage. The logic calculates an exponent delta of Aexp+Bexp−Cexp and determines the number of leading zeroes in C, if C is denormal. The microprocessor accumulates C with the partial products of A and B when the accumulation of C to the product of A and B could result in mass cancellation, when ExpDelta is greater than or equal to −K (where K is related to a width of a datapath in the partial product adder), and when a C is denormal and its number of leading zeroes plus K exceeds −ExpDelta. The strategic use of resources in the partial product adder and second accumulation stage reduces latency.

Claims11

Dependent claims

A method in a microprocessor of executing an FMA instruction having multiplier, multiplicand, and accumulator operands, each having a significand and an exponent, and for handling a special case in which the accumulator operand is denormal and a product of the multiplier and multiplicand operands would result in an underflow, the method comprising:

determining an exponent difference between a sum of the multiplier and multiplicand operand exponents and the accumulator operand exponent;
determining a number of leading zeroes in the denormal accumulator operand significand;
when the number of leading zeroes plus a nonnegative integer constant exceeds the exponent difference, left-shifting the accumulator operand significand to produce a left-shifted accumulator value and accumulating the left-shifted accumulator value to partial products of the multiplier and multiplicand operand significands in a partial product adder;
using a first circuit that employs 2's complement subtraction to generate a first exponent difference value that is a difference between the product of the multiplier and multiplicand exponents and the accumulator exponent and using the first exponent difference value to control a right-shifter that right shifts the accumulator operand significand;
using a second circuit that employs 1's complement subtraction to generate a second exponent difference value that is a difference between the product of the multiplier and multiplicand exponents and the accumulator exponent and using the second exponent difference value to control a left-shifter that left shifts the accumulator operand significand;
and
if a first condition is met, selecting the right-shifted accumulator operand significand to accumulate with the partial products;
and
if a second condition is met, selecting the left-shifted accumulator operand significand to accumulate with the partial products.

6 more elements

A microprocessor comprising:

FMA execution logic configured to execute a floating point multiply-accumulate instruction of the form ±A*B±C, wherein A, B, and C are input multiplier, multiplicand, and accumulator operands, respectively, each having a significand and an exponent;
the FMA execution logic including a partial product adder for adding partial products of A and B;
the partial product adder being configured to accumulate C with the partial products of A and B for a subset of input operand values in which the absolute value of C is smaller than or nearly as small as the absolute value of the product of A and B;
wherein the FMA execution logic is configured to handle a special case in which C is denormal by:
determining an exponent difference between a sum of the A and B exponents and the C exponent;
determining a number of leading zeroes in the denormal C;
when the number of leading zeroes plus a nonnegative integer constant exceeds the exponent difference, then left-shifting C to produce a left-shifted C value that is then accumulated to the partial products of A and B within the partial product adder;
a left shifter configured to left-shift C and a right shifter configured to right-shift C;
a 1's complement subtractor configured to subtract the C exponent from the product exponent, wherein the product exponent is the sum of the A and B exponents, in order to generate a first representation of the exponent difference;
a 2's complement subtractor configured to subtract the C exponent from the product exponent, wherein the product exponent is the sum of the A and B exponents, in order to generate a second representation of the exponent difference, and to feed said second representation to the right shifter;
and
an inverter configured to receive at least a portion of the first representation of the exponent difference generated by the 1's complement subtractor, invert it, and feed the inverted result to the left shifter;
the FMA execution logic being configured to select amongst a group of inputs to accumulate with the partial products of A and B, wherein the group of inputs comprises outputs of the left and right shifters.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/283,606Filed 3 Oct 2016
Published: US 2018/0095749 A15 Apr 2018
Granted: 18 Sep 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06F 7/483
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: computations with numbers represented by a non-linear…
G06F 7/485
Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or…:…
G06F 7/4876
Multiplying; Dividing: multiplying