G06F 2212/6046
Using a specific cache allocation policy other than replacement policy
G06F2212/6046 (Using a specific cache allocation policy other than replacement policy) appears on 119 US grants and 116 published applications in this corpus.
Search patents in G06F- Granted patents
- 119
- Published applications
- 116
- Assignees
- 47
- Inventors
- 297
- Latest grant
- 8 Jul 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2007 | 0 | 1 |
| 2008 | 0 | 0 |
| 2009 | 0 | 1 |
| 2010 | 0 | 0 |
| 2011 | 1 | 1 |
| 2012 | 0 | 4 |
| 2013 | 0 | 1 |
| 2014 | 3 | 7 |
| 2015 | 9 | 16 |
| 2016 | 13 | 17 |
| 2017 | 15 | 10 |
| 2018 | 17 | 18 |
| 2019 | 24 | 14 |
| 2020 | 10 | 12 |
| 2021 | 10 | 5 |
| 2022 | 6 | 1 |
| 2023 | 7 | 2 |
| 2024 | 2 | 0 |
| 2025 | 2 | 2 |
| 2026 | 0 | 4 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- System cache optimizations for deep learning compute engines8 Jul 2025US 12,353,334 B2Intel Corporation
- Memory allocation in a hierarchical memory system6 May 2025US 12,293,227 B2Telefonaktiebolaget LM Ericsson (publ)
- System cache optimizations for deep learning compute engines27 Feb 2024US 11,914,525 B2Intel Corporation
- Cache thrash detection30 Jan 2024US 11,886,354 B1Apple Inc.
- Method and system for performing data movement operations with read snapshot and in place write update14 Nov 2023US 11,816,036 B2Intel Corporation
- Cache level selection16 Jul 2026US 2026/0203216 A1Arm Limited
- Logical Memory Devices with Customizable Latency in Servicing a Host Processor over a Compute Express Link Fabric11 Jun 2026US 2026/0161546 A1Micron Technology, Inc.
- Recovery path cache11 Jun 2026US 2026/0161565 A1Intel Corporation
- Use control method for cache resources and electronic device28 May 2026US 2026/0147710 A1Smarter Silicon (Shanghai) Technologies Co., Ltd.
- Systems and methods for cache entry replacement2 Oct 2025US 2025/0307165 A1Advanced Micro Devices, Inc.
Most cited
By later US patents
- Dynamic memory cache size adjustment in a memory device50US 8,886,911 B2Micron Technology, Inc. · 2014
- Apparatus and method for implementing a multi-level memory hierarchy having different operating modes26US 9,378,142 B2Intel Corporation · 2016
- RE-MRU of metadata tracks to reduce lock contention16US 9,710,398 B2International Business Machines Corporation · 2017
- Method and system for performing data movement operations with read snapshot and in place write update13US 11,816,036 B2Intel Corporation · 2023
- Methods and apparatus for multiple memory maps and multiple page caches in tiered memory11US 9,478,274 B1EMC Corporation · 2016