Logical Memory Devices with Customizable Latency in Servicing a Host Processor over a Compute Express Link Fabric

Abstract

A system having a compute express link fabric having a controller, a plurality of memory devices connected to the compute express link fabric, and a plurality of host processors connected to the compute express link fabric. A logical memory device is attached via the compute express link fabric to a host processor among the plurality of host processors and implemented using memory resources of the memory devices. The controller can, responsive to a request from the host processor, change implementation of the logical memory device, implemented using memory resources of the memory devices, without restarting the system. The logical memory device has, before the request, a first level of latency in servicing the host processor and, after the request, a second level, different from the first level, of latency in servicing the host processor.

Dependencies are inferred from the claim text.