Cache thrash detection
AssigneeApple Inc.
InventorsAnwar Q. Rohillah, Tyler J. Huberty
Life of this patent
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Abstract
Techniques are disclosed relating to cache thrash detection. In some embodiments, cache controller circuitry is configured to monitor and track performance metrics across multiple levels of a cache hierarchy, detect cache thrashing based on one or more performance metrics, and modify a cache insertion policy to mitigate cache thrashing. Disclosed techniques may advantageously detect and reduce or avoid cache thrashing, which may increase processor performance, decrease power consumption for a given workload, or both, relative to traditional techniques.
Claims20
An apparatus, comprising:
- first cache circuitry at a first level in a cache hierarchy;
- second cache circuitry at a second, different level in the cache hierarchy;
- one or more processors configured to execute program instructions that cause access to the first cache circuitry and the second cache circuitry;
- cache controller circuitry configured to:
- over a first set of processor cycles, insert data into the first cache circuitry according to a first cache insertion policy;
- evaluate respective values of a performance metric for the first cache circuitry and for the second cache circuitry;
- and
- in response to detecting that the value of the performance metric for the first cache circuitry does not meet a first threshold and that the value of the performance metric for the second cache circuitry meets a second threshold, determine to replace the first cache insertion policy with a second cache insertion policy over a second set of processor cycles, wherein the second threshold is greater than the first threshold.
A method, comprising:
- executing, by a computing system, program instructions that cause access to a first cache circuitry at a first level in a cache hierarchy and a second cache circuitry at a second, different level in the cache hierarchy;
- inserting, by the computing system, data into the first cache circuitry according to a first cache insertion policy over a first set of processor cycles;
- evaluating, by the computing system, respective values of a performance metric for the first cache circuitry and for the second cache circuitry;
- and
- in response to detecting that the value of the performance metric for the first cache circuitry does not meet a first threshold and that the value of the performance metric for the second cache circuitry meets a second threshold, the computing system determining to replace the first cache insertion policy with a second cache insertion policy over a second set of processor cycles, wherein the second threshold is greater than the first threshold.
A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
- first cache circuitry at a first level in a cache hierarchy;
- second cache circuitry at a second, different level in the cache hierarchy;
- one or more processors configured to execute program instructions that cause access to the first cache circuitry and the second cache circuitry;
- cache controller circuitry configured to:
- over a first set of processor cycles, insert data into the first cache circuitry according to a first cache insertion policy;
- evaluate respective values of a performance metric for the first cache circuitry and for the second cache circuitry;
- and
- in response to detecting that the value of the performance metric for the first cache circuitry does not meet a first threshold and that the value of the performance metric for the second cache circuitry meets a second threshold, determine to replace the first cache insertion policy with a second cache insertion policy over a second set of processor cycles, wherein the second threshold is greater than the first threshold.
Dependencies are inferred from the claim text.