Cache level selection
AssigneeArm Limited
InventorsMatthew James HORSNELL, Thomas Philip SPEIER, Salil Ramchandra AKERKAR
Life of this patent
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Abstract
An apparatus comprises cache control circuitry to allocate, to a cache hierarchy comprising a plurality of levels of cache, one or more materialised cache lines corresponding to a region of address space indicated by software-provided information, each materialised cache line specifying a predetermined value as cached data; and cache level selection circuitry to select, based on a size of the region of address space indicated by the software-provided information, at least one target level of the plurality of levels of cache to which the one or more materialised cache lines are to be allocated.
Claims17
An apparatus comprising:
- cache control circuitry configured to allocate, to a cache hierarchy comprising a plurality of levels of cache, one or more materialised cache lines corresponding to a region of address space indicated by software-provided information, each materialised cache line specifying a predetermined value as cached data;
- and
- cache level selection circuitry configured to select, based on a size of the region of address space indicated by the software-provided information, at least one target level of the plurality of levels of cache to which the one or more materialised cache lines are to be allocated.
A chip-containing product comprising the system of claim 15, wherein the system is assembled on a further board with at least one other product component.
A method comprising:
- allocating, to a cache hierarchy comprising a plurality of levels of cache, one or more materialised cache lines corresponding to a region of address space indicated by software-provided information, each materialised cache line specifying a predetermined value as cached data;
- and
- selecting, based on a size of the region of address space indicated by the software-provided information, at least one target level of the plurality of levels of cache to which the one or more materialised cache lines are to be allocated.
A non-transitory computer-readable medium storing computer-readable code for fabrication of an apparatus comprising:
- cache control circuitry configured to allocate, to a cache hierarchy comprising a plurality of levels of cache, one or more materialised cache lines corresponding to a region of address space indicated by software-provided information, each materialised cache line specifying a predetermined value as cached data;
- and
- cache level selection circuitry configured to select, based on a size of the region of address space indicated by the software-provided information, at least one target level of the plurality of levels of cache to which the one or more materialised cache lines are to be allocated.
Dependencies are inferred from the claim text.