G06F 2207/5063
2-input gates, i.e. only using 2-input logical gates
Official title: 2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder
G06F2207/5063 (2-input gates, i.e. only using 2-input logical gates) appears on 54 US grants and 29 published applications in this corpus.
Search patents in G06F- Granted patents
- 54
- Published applications
- 29
- Assignees
- 36
- Inventors
- 87
- Latest grant
- 20 Jun 2023
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 1 | 0 |
| 1991 | 2 | 0 |
| 1992 | 2 | 0 |
| 1993 | 2 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 2 | 0 |
| 1997 | 6 | 0 |
| 1998 | 3 | 0 |
| 1999 | 0 | 0 |
| 2000 | 2 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 1 |
| 2003 | 8 | 4 |
| 2004 | 0 | 4 |
| 2005 | 1 | 0 |
| 2006 | 4 | 1 |
| 2007 | 0 | 1 |
| 2008 | 0 | 1 |
| 2009 | 0 | 2 |
| 2010 | 1 | 0 |
| 2011 | 1 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 1 | 2 |
| 2015 | 1 | 0 |
| 2016 | 0 | 1 |
| 2017 | 1 | 0 |
| 2018 | 1 | 1 |
| 2019 | 3 | 4 |
| 2020 | 3 | 3 |
| 2021 | 2 | 2 |
| 2022 | 1 | 0 |
| 2023 | 2 | 1 |
| 2024 | 0 | 0 |
| 2025 | 0 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- Concurrent multi-bit adder20 Jun 2023US 11,681,497 B2GSI Technology, Inc.
- Adder circuitry for very large integers30 May 2023US 11,662,979 B2Intel Corporation
- Prefix network-directed addition17 May 2022US 11,334,318 B2Intel Corporation
- Parallel-prefix adder and method18 May 2021US 11,010,133 B2Marvell Asia Pte Ltd
- FPGA logic cell with improved support for counters2 Mar 2021US 10,936,286 B2Microsemi SoC Corporation
- Multiplier with a new Partial Product Generation Method3 Jul 2025US 2025/0217109 A1
- Concurrent multi-bit adder19 Oct 2023US 2023/0333815 A1GSI Technology, Inc.
- Concurrent multi-bit adder18 Mar 2021US 2021/0081173 A1GSI Technology, Inc.
- Adder circuitry for very large integers11 Mar 2021US 2021/0075425 A1Intel Corporation
- Parallel-prefix adder and method22 Oct 2020US 2020/0334014 A1Globalfoundries Inc.
Most cited
By later US patents
- Method and apparatus for designing circuits for wave pipelining258US 5,796,624 AThe Research Foundation of State University of New York · 1998
- Cycle segmented prefix circuits123US 6,609,189 B1Yale University · 2003
- Method of operation of arithmetic and logic unit, storage medium, and arithmetic and logic unit54US 6,028,987 ASony Corporation · 2000
- Complementary field-effect transistor logic circuits for wave pipelining34US 5,528,177 AThe Research Foundation of State University of New York · 1996
- High-performance differential cascode voltage switch with pass gate logic elements34US 5,777,491 AInternational Business Machines Corporation · 1998