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US 11,334,318 B2Granted
Prefix network-directed addition
AssigneeIntel Corporation
InventorsMartin Langhammer, Bogdan Mihai Pasca, Sergey Vladimirovich Gribok
Life of this patent
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Abstract
The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision is restructured so that a set of sub-adders performs the arithmetic on a respective segment of the operands. More specifically, the adder is restructured, and a decoder determines a generate signal and a propagate signal for each of the sub-adders and routes the generate signal and the propagate signal to a prefix network. The prefix network determines respective carry bit(s), which carries into and/or select a sum at a subsequent sub-adder.
Claims20
Adder circuitry on an integrated circuit device, the adder circuitry comprising:
- first input circuitry configured to receive a first input having a first set of bits;
- second input circuitry configured to receive a second input having a second set of bits;
- a first decoder coupled to the first input circuitry and to the second input circuitry, wherein the first decoder is configured to receive a first subset of the first set of bits and a first subset of the second set of bits and to determine a generate signal and a propagate signal based at least in part on the first subset of the first set of bits and the first subset of the second set of bits;
- a prefix network coupled to the first decoder, wherein the prefix network is configured to determine a carry out signal based at least in part on the generate signal and the propagate signal, wherein the prefix network comprises first combinatorial circuitry;
- second combinatorial circuitry coupled to the prefix network, wherein the second combinatorial circuitry comprises sub-adder circuitry coupled to the first input circuitry, the second input circuitry, and the prefix network, wherein the sub-adder circuitry is configured to determine a portion of a sum of the first set of bits and the second set of bits by adding a second subset of the first set of bits, a second subset of the second set of bits, and the carry out signal;
- and
- a delay chain coupled between the first input circuitry and the sub-adder circuitry and between the second input circuitry and the sub-adder circuitry, wherein the delay chain is configured to delay receipt of the second subset of the first set of bits and the second subset of the second set of bits at the sub-adder circuitry based in part on a latency of the prefix network.
4 more elements
Adder circuitry on an integrated circuit device, the adder circuitry comprising:
- first input circuitry configured to receive a first input having a first set of bits;
- second input circuitry configured to receive a second input having a second set of bits;
- a first decoder coupled to the first input circuitry and to the second input circuitry, wherein:
- the first decoder is configured to:
- receive a first subset of the first set of bits and a first subset of the second set of bits;
- determine a precursor to a propagate signal based in part on a sum of the first subset of the first set of bits and the first subset of the second set of bits with a carry-in signal;
- and
- determine a generate signal based at least in part on the first subset of the first set of bits and the first subset of the second set of bits;
- the first decoder comprises an AND gate configured to:
- receive a complement of the generate signal and the precursor to the propagate signal;
- and
- determine the propagate signal based in part on a logical AND of the complement of the generate signal and the precursor to the propagate signal;
- a prefix network coupled to the first decoder, wherein the prefix network is configured to determine a carry out signal based at least in part on the generate signal and the propagate signal, wherein the prefix network comprises first combinatorial circuitry;
- and
- second combinatorial circuitry coupled to the prefix network, wherein the second combinatorial circuitry is configured to determine a portion of a sum of the first set of bits and the second set of bits based at least in part on the carry out signal.
12 more elements
Adder circuitry on an integrated circuit device, the adder circuitry comprising:
- first input circuitry configured to receive a first input having a first set of bits;
- second input circuitry configured to receive a second input having a second set of bits;
- a first decoder coupled to the first input circuitry and to the second input circuitry, wherein the first decoder is configured to receive a first subset of the first set of bits and a first subset of the second set of bits and to determine a generate signal and a propagate signal based at least in part on the first subset of the first set of bits and the first subset of the second set of bits;
- a prefix network coupled to the first decoder, wherein the prefix network is configured to recursively determine a carry out signal based at least in part on the generate signal and the propagate signal, wherein the prefix network comprises:
- first combinatorial circuitry;
- a second decoder configured to receive a first subset of the generate signal and a first subset of the propagate signal and to determine an additional generate signal and an additional propagate signal based at least in part on the first subset of the generate signal and the first subset of the propagate signal;
- an additional prefix network coupled to the second decoder, wherein the additional prefix network is configured to determine an additional carry out signal based at least in part on the additional generate signal and the additional propagate signal, wherein the additional prefix network comprises second combinatorial circuitry;
- and
- third combinatorial circuitry coupled to the additional prefix network, wherein the third combinatorial circuitry is configured to determine the carry out signal based at least in part on the additional carry out signal;
- and
- fourth combinatorial circuitry coupled to the prefix network, wherein the fourth combinatorial circuitry is configured to determine a portion of a sum of the first set of bits and the second set of bits based at least in part on the carry out signal.
8 more elements
Dependencies are inferred from the claim text.