Parallel-prefix adder and method

An adder comprising:

• a primary carry bit generation circuit configured to:
• generate first carry bits for a first number of pairs of bits from first and second operands;
• and
• generate second carry bits for a second number of pairs of bits from the first and second operands, the second number of pairs being different than the first number of pairs;
• wherein a first ratio of the second carry bits to the second number of pairs is different than a second ratio of the first carry bits to the first number of pairs;
• and
• wherein the first and second number of pairs depend on whether the first and second operands are even or odd numbers;
• and
• a summing circuit configured to:
• generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits;
• and
• generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

A method comprising:

• generating first carry bits for a first number of pairs of bits from first and second operands;
• generating second carry bits for a second number of pairs of bits from the first and second operands, the second number of pairs being different than the first number of pairs;
• generating first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits;
• and
• generating second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs;
• wherein a first ratio of the second carry bits to the second number of pairs is different than a second ratio of the first carry bits to the first number of pairs;
• and
• wherein the first and second number of pairs depend on whether the first and second operands are even or odd numbers.