Cornami, Inc.
Dallas, TX, US· latest recorded location
Cornami, Inc. is named on 33 US grants and 46 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 33
- Published applications
- 46
- Inventors
- 27
- Granted in 2026 so far
- 2
- Most recent grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2016 | 0 | 1 |
| 2017 | 5 | 4 |
| 2018 | 4 | 4 |
| 2019 | 2 | 3 |
| 2020 | 2 | 1 |
| 2021 | 1 | 5 |
| 2022 | 3 | 3 |
| 2023 | 4 | 5 |
| 2024 | 8 | 9 |
| 2025 | 2 | 3 |
| 2026 | 2 | 8 |
By publication year. 2026 runs to 8 Oct.
Technology areas
Share of 79 documents
- G06FComputing and data processing71
- H03KPulse technique14
- H03MCoding14
- Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information14
- H04LDigital communication13
- G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial11
- G06NAI and machine learning6
- G06VImage and video recognition5
Recent patents
- Method and system for reducing FFT calculations in FHE bootstrapping15 Sep 2026US 12,737,468 B2
- Method and system for providing fault tolerant layout of massively parallel processing array8 Sep 2026US 12,730,956 B2
- Reconfigurable processor circuit architecture4 Nov 2025US 12,461,890 B2
- Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm6 May 2025US 12,293,188 B2
- Reconfigurable arithmetic engine circuit31 Dec 2024US 12,182,063 B2
- Systems and methods to efficiently process matrices in llms using singular value decomposition8 Oct 2026US 2026/0310748 A1
- Cache architecture for a massively parallel processing array20 Aug 2026US 2026/0244572 A1
- Method and system for fault tolerant rerouting for massively parallel processing array6 Aug 2026US 2026/0228095 A1
- Method and system for providing efficient quantum proof encryption using boolean gates with reduced bootstrapping23 Jul 2026US 2026/0213918 A1
- Method and system for reduction of ciphertext matrix computation and bootstrapping in secure llm28 May 2026US 2026/0149565 A1
Most cited
By later US patents
- Method, apparatus, and computer-readable medium for parallelization of a computer program on a plurality of computing cores15US 9,760,530 B22017
- Parallel processing of data having data dependencies for accelerating the launch and performance of operating systems and other computing applications9US 11,669,526 B22023
- Parallel processing of data having data dependencies for accelerating the launch and performance of operating systems and other computing applications6US 9,647,686 B22017
- Method and apparatus for a general-purpose multiple-core system for implementing stream-based computations4US 10,073,700 B22018
- Hardware task manager4US 9,665,397 B22017