Cache architecture for a massively parallel processing array
AssigneeCornami, Inc.
InventorMartin Alan Franz, II
Life of this patent
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Abstract
A cache architecture for an array of identical cores arranged in a grid. Each of the cores include interconnections to neighboring cores in the grid, a memory, and an algorithmic logic unit. A first core of the array is configured to receive a memory access request for data from at least one core of the array of cores configured to perform a computational operation. A second core of the array is configured to determine whether the requested data is present in a cache memory via a cache index including addresses in the cache memory. A third core of the array is configured as the cache memory. The memory of the third core is used as the cache memory. An address of the requested data from the cache index is passed to the third core to output the requested data.
Claims19
A cache architecture for an array of identical cores arranged in a grid, each of the cores including interconnections to neighboring cores in the grid, a memory, and an algorithmic logic unit, the cache architecture comprising:
- a first core of the array configured to receive a memory access request for data from at least one core of the array of cores configured to perform a computational operation;
- a second core of the array configured to determine whether the requested data is present in a cache memory via a cache index including addresses in the cache memory;
- and
- a third core of the array configured as the cache memory, wherein the memory of the third core is used as the cache memory, wherein an address of the requested data from the cache index is passed to the third core to output the requested data.
A method of providing a cache memory for an array of cores arranged in a grid, each of the cores including interconnections to neighboring cores in the grid, a memory, and an algorithmic logic unit, the method comprising:
- configuring a first core of the array to receive a memory access request for data from at least one core of the array of cores configured to perform a computational operation;
- configuring a second core of the array to determine whether the requested data is present in a cache memory via a cache index including addresses in the cache memory;
- and
- configuring a third core of the array as the cache memory, wherein the memory of the third core is used as the cache memory;
- and
- passing an address of the requested data from the cache index to the third core to output the requested data.
A system on chip comprising:
- a high bandwidth memory;
- and
- a die including an array of cores coupled to an interconnection network, the interconnection network allowing access to the high bandwidth memory, each of the cores in the array of cores including a memory and an algorithmic logic unit, wherein:
- a first core of the array is configured to receive a memory access request for data from at least one core of the array of cores configured to perform a computational operation;
- a second core of the array is configured to determine whether the requested data is present in a cache memory via a cache index including addresses in the cache memory;
- and
- a third core of the array is configured as the cache memory, wherein the memory of the third core is used as the cache memory, wherein an address of the requested data from the cache index is passed to the third core to output the requested data.
Dependencies are inferred from the claim text.