Reconfigurable processor circuit architecture

A reconfigurable processor circuit comprising:

• a first interconnection network;
• a second interconnection network;
• a processor coupled to the first interconnection network;
• and
• a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network configured to couple adjacent computational cores of the plurality of computational cores, each computational core comprising:
• a memory circuit;
• and
• a reconfigurable arithmetic circuit comprising:
• at least one input reordering queue configured to store a plurality of inputs, the at least one input reordering queue further comprising input reordering logic circuitry configured to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuit and an adjacent reconfigurable arithmetic circuit of the plurality of computational cores;
• a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the at least one input reordering queue, the plurality of operating modes comprising a fixed-point operating mode and a floating point operating mode;
• a multiplier shifter and combiner network coupled to the configurable multiplier, the multiplier shifter and combiner network comprising:
• a shifter circuit;
• and
• a plurality of series-coupled adder circuits coupled to the shifter circuit;
• an accumulator circuit;
• at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit;
• a compare circuit coupled to the at least one input reordering queue, the compare circuit configurable to perform modulo counting;
• and
• at least one output reorder queue coupled to receive and configured to reorder a plurality of outputs from the reconfigurable arithmetic circuit and the adjacent reconfigurable arithmetic circuit of the plurality of computational cores.

A reconfigurable processor circuit comprising:

• a first interconnection network;
• a second interconnection network;
• a third interconnection network;
• a processor coupled to the first interconnection network;
• and
• a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network configured to directly couple adjacent computational cores of the plurality of computational cores, each computational core comprising:
• a memory circuit;
• and
• a reconfigurable arithmetic circuit comprising:
• at least one input reordering queue;
• an accumulator circuit;
• a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the at least one input reordering queue, the plurality of operating modes comprising a fixed-point operating mode and a floating point operating mode;
• a multiplier shifter and combiner network coupled to the configurable multiplier, the multiplier shifter and combiner network comprising:
• a shifter circuit;
• and
• a plurality of series-coupled adder circuits coupled to the shifter circuit;
• at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit;
• and
• a comparator circuit coupled to the at least one input reordering queue, the comparator circuit configurable to perform modulo counting;
• wherein the third interconnection network comprises a plurality of direct connections linking adjacent reconfigurable arithmetic circuits of the plurality of computational cores, and wherein the third interconnection network is configurable to selectively couple the multiplier shifter and combiner network to one or more adjacent reconfigurable arithmetic circuits.