H03M 13/1122
Storing only the first and second minimum values per check node
Official title: {storing only the first and second minimum values per check node}
H03M13/1122 (Storing only the first and second minimum values per check node) appears on 110 US grants and 119 published applications in this corpus.
Search patents in H03M- Granted patents
- 110
- Published applications
- 119
- Assignees
- 84
- Inventors
- 238
- Latest grant
- 11 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 1 |
| 2004 | 0 | 2 |
| 2005 | 0 | 2 |
| 2006 | 1 | 4 |
| 2007 | 3 | 7 |
| 2008 | 3 | 8 |
| 2009 | 2 | 5 |
| 2010 | 4 | 12 |
| 2011 | 4 | 5 |
| 2012 | 12 | 3 |
| 2013 | 8 | 6 |
| 2014 | 8 | 9 |
| 2015 | 13 | 4 |
| 2016 | 3 | 12 |
| 2017 | 5 | 2 |
| 2018 | 7 | 6 |
| 2019 | 8 | 5 |
| 2020 | 6 | 3 |
| 2021 | 0 | 1 |
| 2022 | 4 | 4 |
| 2023 | 2 | 3 |
| 2024 | 5 | 2 |
| 2025 | 8 | 11 |
| 2026 | 3 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Decoder circuit and decoding method capable of reducing number of read/write of memory to reduce power consumption11 Aug 2026US 12,706,614 B2Silicon Motion, Inc.
- LDPC decoder and minimum value searching method3 Mar 2026US 12,567,872 B2Realtek Singapore Private Limited
- Compressing check node unit parameters in low-density parity-check codes in non-volatile memory devices6 Jan 2026US 12,519,489 B2SK hynix Inc.
- Adaptive scaling of parity check messages for LDPC decoding9 Sep 2025US 12,413,246 B2Airbus Defence and Space GmbH
- Technique to perform decoding of wireless communications signal data19 Aug 2025US 12,395,189 B2NVIDIA Technologies, Inc.
- Decoder circuit and decoding method capable of reducing number of read/write of memory to reduce power consumption23 Apr 2026US 2026/0113058 A1Silicon Motion, Inc.
- Layered decoding of low density parity check (ldpc) codes19 Mar 2026US 2026/0081621 A1Samsung Electronics Co., Ltd.
- Decoding processing method and apparatus, and storage medium and electronic apparatus11 Dec 2025US 2025/0379680 A1Sanechips Technology Co., Ltd.
- Check node data compression in memory systems31 Jul 2025US 2025/0247112 A1SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Compressing check node unit parameters in low-density parity-check codes in non-volatile memory devices17 Jul 2025US 2025/0233600 A1SK hynix Inc.
Most cited
By later US patents
- Reduced-complexity decoding of parity check codes161US 7,752,523 B1Marvell International Ltd. · 2010
- Method and device for decoding LDPC codes and communication apparatus including such device73US 8,291,284 B2Commissariat A L' Energie Atomique · 2012
- Encoder and decoder by LDPC coding55US 8,140,930 B1NEC Corporation · 2012
- Semi-systolic architecture for decoding error-correcting codes53US 5,157,671 ASpace Systems/Loral, Inc. · 1992
- Memory efficient LDPC decoding methods and apparatus40US 7,127,659 B2QUALCOMM Incorporated · 2006