Decoder circuit and decoding method capable of reducing number of read/write of memory to reduce power consumption

A decoder circuit, comprising:

• a channel value memory, for receiving and storing an input data as a channel value, the channel value being stored in the channel value memory in a form of a sign bit with multiple magnitude bits;
• a sign memory, for storing a sign value;
• a gradient descent bit memory, for storing a difference information corresponding to the channel value;
• a variable node unit, coupled to the channel value memory, the sign memory, and the gradient descent bit memory, for generating a first output value and a second output value according to the channel value;
• a first barrel shifter, coupled to the variable node unit, for converting the first output value from a variable node domain to a check node domain to generate a converted first output value;
• a check node unit, coupled to the first barrel shifter, for generating a check-to-variable message based on the converted first output value or the sign value stored in the sign memory;
• a second barrel shifter, coupled to the check node unit, for converting the check-to-variable message from the check node domain to the variable node domain to generate a converted check-to-variable message to the variable node unit;
• and
• a decision bit output unit, coupled to the gradient descent bit memory and the channel value memory, for generating and determining an output data according to the channel value in the channel value memory and the difference information corresponding to the channel value stored in the gradient descent bit memory.