Encoder and decoder by LDPC coding
AssigneeNEC Corporation
InventorTsuguo Maru
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Abstract
The present invention is intended to provide an LDPC coding scheme which is capable of efficiently implementing a high-performance and high-speed encoder and decoder of an error correcting code suitable for the field of communications such as mobile communications. As to the configuration, a Tanner graph for representing codes with variable nodes and check nodes is used to classify the individual nodes into a plurality of categories. For calculating a probability propagation in iterative decoding, weighting previously determined for each category is performed on a log-likelihood ratio (LLR) subjected to propagation.
Claims21
An LDPC decoder, using a Tanner graph in an LDPC coding scheme, wherein each node can be classified into a plurality of categories, said decoder thus configured is characterized by performing weighting previously determined for each of the categories for a log-likelihood ratio (hereinafter abbreviated as “LLR”) subjected to a propagation in a probability propagation calculation in iterative decoding.
An LDPC decoder, using a Tanner graph in an LDPC coding scheme, wherein each node forming part of a graph can be classified into a plurality of groups according to a column weight of a test matrix thereof, said decoder configured to be characterized by performing the weighting determined for each of the groups for a log-likelihood ratio (hereinafter abbreviated as “LLR”) subjected to propagation in a probability propagation calculation in iterative decoding.
An LDPC decoder, using a Tanner graph in an LDPC coding scheme, wherein each node can be classified into a plurality of categories, said decoder configured to be characterized by changing the number of divided memory banks for storing a log-likelihood ratio (LLR) subjected to a propagation in accordance with a weight distribution of a test matrix belonging to each category to enable a parallel access to the log-likelihood ratio.
An LDPC encoder configured to be characterized by having first means 1 for producing matrixes A, B, T having a relationship of an upper triangular zero matrix represented by:
- H
- =
- [
- A
- B
- T
- C
- D
- E
- ]
- [
- Equation
-
-
- 1
- ]
- including lower triangular matrix T having 1's at diagonal elements by a matrix manipulation of test matrix H, further having second means for producing matrix F represented by:
- F=(−E·T−1·B+D)−1·(E·T−1·A−C) [Equation 2]
- from the upper triangular zero matrix, wherein said first means and said second means are previously calculated offline processes, and have first memory for accumulating the positions of elements having 1's in resulting matrix F in the form of an index, second memory for storing information bit series S, and a first row counter, having a first circuit for producing first parity series p1 by taking an exclusive OR of the output of said second memory further addressed by an index output by said first memory addressed by said first row counter, having third memory for storing a series represented by:
- −A·sT−B·p1T [Equation 3]
- by taking a product of parity series p1 and matrix B resulting from the offline process, taking a product of information bit series S and matrix A resulting from the offline process, and taking an exclusive OR of the products, having fourth memory for accumulating the positions of elements of matrix T having 1's resulting from the offline process in the form of an index, fifth memory for storing second parity series p2, and a second row counter, and having a second circuit for taking an exclusive OR of the output of said fifth memory sequentially read and addressed further by an index output by said fourth memory addressed by said second row counter, and the output of said third memory addressed by said second row counter to produce second parity series p2, and writing said fourth memory written and addressed by said second row counter, wherein encoding processing is performed by the offline process and an online process by the second and second circuits.
An LDPC decoder using a Tanner graph which represents a code with a variable node and a check node, characterized by comprising:
- a first variable node memory including a plurality of memory banks for storing a log-likelihood ratio subjected to a propagation classified into a plurality of categories on a category-by-category basis;
- a second variable node memory including a plurality of memory banks for storing a weighting value for each of the plurality of categories on a category-by-category basis;
- a weighting processing unit for determining a weighting value for each category stored in said second variable node memory in accordance with the log-likelihood ratio subjected to the propagation;
- and
- check node processing means for performing a probability propagation calculation in iterative decoding from stored contents of each category in said first variable node memory and second variable node memory, to output to said first variable node memory and to weighting processing unit, as the log-likelihood ratio subjected to the propagation.
Dependencies are inferred from the claim text.