Compressing check node unit parameters in low-density parity-check codes in non-volatile memory devices

A system for improving a performance of an iterative decoder in a non-volatile memory, comprising:

• a processor and a memory including instructions stored thereupon, wherein the instructions upon execution by the processor cause the processor to:
• receive a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code;
• perform, on the noisy codeword for a first iteration, a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent a parity matrix of the LDPC code,
• wherein, as part of performing the message passing algorithm, at least one check node of the plurality of check nodes is configured to:
• receive, each of a plurality of messages from a corresponding variable node of a subset of the plurality of variable nodes connected to the at least one check node, each of the plurality of messages comprising a sign and a magnitude,
• identify (i) a first minimum value corresponding to a smallest magnitude amongst the plurality of messages, (ii) a second minimum value, greater than the first minimum value, corresponding to a second smallest magnitude amongst the plurality of messages, (iii) a first index associated with the first minimum value, and (iv) a second index associated with the second minimum value,
• map a concatenation of the smallest magnitude, the second smallest magnitude, the first index, and the second index to a bit string, wherein a length of the bit string is less than a length of the concatenation, and
• store the bit string in a check node unit (CNU) register;
• and
• perform, on the noisy codeword for a remaining number of iterations, the message passing algorithm to determine a candidate version of the transmitted codeword.

A non-transitory computer-readable storage medium having instructions stored thereupon for improving performance of an iterative decoder in a non-volatile memory device, comprising:

• instructions for receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code;
• instructions for performing, on the noisy codeword for a first iteration, a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent a parity matrix of the LDPC code,
• wherein, as part of performing the message passing algorithm, at least one check node of the plurality of check nodes is configured to:
• receive, each of a plurality of messages from a corresponding variable node of a subset of the plurality of variable nodes connected to the at least one check node, each of the plurality of messages comprising a sign and a magnitude,
• identify (i) a first minimum value corresponding to a smallest magnitude amongst the plurality of messages, (ii) a second minimum value, greater than the first minimum value, corresponding to a second smallest magnitude amongst the plurality of messages, (iii) a first index associated with the first minimum value, and (iv) a second index associated with the second minimum value,
• map a concatenation of the smallest magnitude, the second smallest magnitude, the first index, and the second index to a bit string, wherein a length of the bit string is less than a length of the concatenation, and
• store the bit string in a check node unit (CNU) register;
• and
• instructions for performing, on the noisy codeword for a remaining number of iterations, the message passing algorithm to determine a candidate version of the transmitted codeword.