G06F 8/4441
Reducing the execution time required by the program code
Official title: {Reducing the execution time required by the program code}
G06F8/4441 (Reducing the execution time required by the program code) appears on 1,158 US grants and 1,184 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,158
- Published applications
- 1,184
- Assignees
- 263
- Inventors
- 2,132
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 2 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 6 | 0 |
| 1998 | 10 | 0 |
| 1999 | 13 | 0 |
| 2000 | 10 | 0 |
| 2001 | 20 | 8 |
| 2002 | 8 | 25 |
| 2003 | 16 | 32 |
| 2004 | 16 | 34 |
| 2005 | 18 | 40 |
| 2006 | 36 | 16 |
| 2007 | 18 | 31 |
| 2008 | 24 | 36 |
| 2009 | 21 | 31 |
| 2010 | 20 | 41 |
| 2011 | 14 | 38 |
| 2012 | 40 | 45 |
| 2013 | 64 | 60 |
| 2014 | 68 | 69 |
| 2015 | 76 | 74 |
| 2016 | 91 | 74 |
| 2017 | 71 | 50 |
| 2018 | 67 | 77 |
| 2019 | 83 | 77 |
| 2020 | 66 | 66 |
| 2021 | 60 | 54 |
| 2022 | 58 | 61 |
| 2023 | 55 | 50 |
| 2024 | 44 | 42 |
| 2025 | 31 | 29 |
| 2026 | 30 | 24 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Method and system for determining an expected execution time for a compiled graph using a cost model6 Oct 2026US 12,754,725 B2Moreh Corp.
- Graph analysis and manipulation29 Sep 2026US 12,748,576 B2Microsoft Technology Licensing, LLC
- Runtime optimization of computations of an artificial neural network compiled for execution on a deep learning accelerator1 Sep 2026US 12,725,026 B2Micron Technology, Inc.
- Range slots for deterministic finite automatons in a regular expression accelerator25 Aug 2026US 12,717,845 B2
- Method and system for implementing binary arrays18 Aug 2026US 12,710,928 B2
- Batch-Parallel Gradient Computation via Matrix Multiplication on Reconfigurable Dataflow Processors1 Oct 2026US 2026/0299968 A1SambaNova Systems, Inc.
- Hardware-optimized, symmetric, high-performance auto-parallelization system with loop-level parallelization, and method thereof24 Sep 2026US 2026/0288434 A1Mynatix AG
- Boosting performance of ai/ml hpc workloads17 Sep 2026US 2026/0277703 A1Hewlett Packard Enterprise Development LP
- Dynamic compiler techniques3 Sep 2026US 2026/0259715 A1NVIDIA Corporation
- Dynamic compiler techniques3 Sep 2026US 2026/0259716 A1NVIDIA Corporation
Most cited
By later US patents
- Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector426US 8,417,921 B2Apple Inc. · 2013
- Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture418US 8,555,037 B2Apple Inc. · 2013
- Method for compiling high level programming languages into an integrated processor with reconfigurable logic219US 5,966,534 A1999
- Purity analysis using white list/black list analysis207US 9,417,859 B2Microsoft Technology Licensing, LLC · 2016
- Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications188US 5,704,053 AHewlett-Packard Company · 1997