A symmetric auto-compiler system for hardware-optimized auto-parallelization of a program code for execution by a multi-core or multi-processor parallel processing system having a plurality of processing units simultaneously processing instructions on data in the parallel processing system by executing the program code, the auto-compiler system comprising means for transforming a serial source code of the program code written in a programming language into a parallel processing machine code comprising a number of instructions executable by the plurality of processing units of the parallel processing system or controlling the operation of the plurality of processing units,
- wherein the parallel processing system comprise memory units comprising at least main execution memory units comprising a plurality of memory banks for holding data of at least parts of the processing code, and transition buffer units comprising high speed memory for storing starting locations of the processing code and data segments at least comprising branch or jump instructions and/or used memory references and data values, wherein the main execution memory units provide a slower access time than the transition buffer units,
- wherein the execution of the processing code by the parallel processing system comprises the occurrence of latency times, the latency times being given by idle time of a processing unit between transmitting data back after having processed a specific block of instructions of the processing code on the data by the processing unit and receiving data necessary for execution of a consecutive block of instructions of the processing code by said processing units,
- wherein the compiler system comprises a parser module for translating the serial source code into a code with a flow of elementary instructions executable by the processing units, the elementary instructions selectable out of a limited, processing-unit-specific set of elementary instructions and the elementary instructions comprising exclusively elementary arithmetic and logic operations and/or elementary control and memory operations for the number of processing units,
- wherein the parser module comprises means for partitioning the code of said elementary instructions into computation block nodes, each computation block node consisting of a smallest possible segmentation of a non-further decomposable sequence of elementary instructions of the code processable by a single processing unit, the smallest possible segmentation of the elementary instructions being characterized by a sequence of elementary instructions framed by consecutive read and write instructions, said sequence being not further decomposable by smaller sequences of elementary instructions between consecutive read and write instructions, and the read and write instructions needed to receive data required for processing said sequence of elementary instructions by the processing unit and transmit back data after processing by the sequence;
- wherein the compiler system comprises a matrix builder for generating matrices out of computation chains portioned from the code, the matrices comprising computation matrices and transfer matrices and task matrices, wherein each column within a computation matrix comprises computation block nodes being simultaneously processable based on executability of read and write instructions transferring data required for processing of the computation block nodes, wherein the transfer matrix contains to each computation block nodes transfer and process properties at least characterizing data transfer properties from one to a consecutive computation block node at least comprising data size of transmitted data and identification of a source computation block node and target computation block node of the data transfer and/or process characteristics on one of the plurality of processing units,
- wherein tasks of a task matrix are formed by the matrix builder wherein in case of computation block nodes each having a different read associated, the tasks are formed by splitting the computation block nodes of a column of the computation matrix evenly to the number of the plurality of symmetric processing units forming for each of the plurality of processing unit per column of the computation matrix one task, and splitting remaining computation block nodes based on a predefined scheme to at least a part of said tasks, wherein in case of computation block nodes at least partially having a read with identical data transferred, the tasks are formed by minimizing the number of reads uniformly or essentially uniformly over the number of processing units and/or if a predefined offset value is exceeded by minimizing an integrated processing time uniformly over each of the processing units,
- wherein the compiler system comprises an optimizer module using a matrix optimization technique minimizing an aggregated occurring latency time integrating all occurring latency times by providing an optimized structure of the tasks within the task matrix, wherein each column of the task matrix forms a computation chain by one or more tasks creating an ordered flow of computation block nodes to be executed by one of the plurality of processing units,
- wherein the compiler system comprises a code generator for generating the parallel processing machine code for the plurality of processing units with an optimized aggregated latency time based on the computation chains given by the optimized task matrix.