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US 2026/0259716 A1Published application
Dynamic compiler techniques
AssigneeNVIDIA Corporation
InventorsVinod Grover, Thibaut Lutz
Life of this patent
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Abstract
Compiler techniques for inline parallelism and re-targetable parallel runtime execution of logic iterators enable selection thereof from the source code or dynamically during object-code execution.
Claims20
One or more processors, comprising:
- circuitry to:
- receive source code including a portion of the source code and a specifier indicating a second processor different from a first processor for the portion of the source code;
- generate an intermediate representation of the portion of the source code;
- compile the source code into a first portion of machine code for execution on the first processor;
- cause execution of the first portion of machine code on the first processor;
- based at least in part on the specifier indicating the second processor, compile the intermediate representation into a second portion of machine code for execution on the second processor;
- and
- cause the second processor to execute the second portion of machine code.
5 more elements
A method, comprising:
- receiving source code including a portion of the source code and a specifier indicating a second processor different from a first processor for the portion of the source code;
- generating, by a compiler, an intermediate representation of the portion of the source code;
- compiling, by the compiler, the source code into a first portion of machine code for execution on the first processor;
- causing, by a runtime environment, execution of the first portion of machine code on the first processor;
- based at least in part on the specifier indicating the second processor, compiling the intermediate representation into a second portion of machine code for execution on the second processor;
- and
- causing the second processor to execute the second portion of machine code.
4 more elements
A system, comprising:
- a first processor;
- a second processor;
- and
- a non-transitory computer-readable medium storing instructions executable by at least one of the first and second processors to:
- receive source code including a portion of the source code and a specifier indicating the second processor for the portion of the source code;
- generate an intermediate representation of the portion of the source code;
- compile the source code into a first portion of machine code for execution on the first processor;
- cause execution of the first portion of machine code on the first processor;
- based at least in part on the specifier indicating the second processor, compile the intermediate representation into a second portion of machine code for execution on the second processor;
- and
- cause the second processor to execute the second portion of machine code.
8 more elements
Dependencies are inferred from the claim text.