G06F 2213/2412
Dispatching of interrupt load among interrupt handlers in processor system or interrupt
Official title: Dispatching of interrupt load among interrupt handlers in processor system or interrupt controller
G06F2213/2412 (Dispatching of interrupt load among interrupt handlers in processor system or interrupt) appears on 18 US grants and 14 published applications in this corpus.
Search patents in G06F- Granted patents
- 18
- Published applications
- 14
- Assignees
- 9
- Inventors
- 31
- Latest grant
- 7 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2001 | 1 | 0 |
| 2002 | 1 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 1 |
| 2007 | 0 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 1 | 1 |
| 2014 | 2 | 1 |
| 2015 | 2 | 2 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 2 |
| 2019 | 2 | 3 |
| 2020 | 3 | 2 |
| 2021 | 1 | 0 |
| 2022 | 0 | 1 |
| 2023 | 2 | 1 |
| 2024 | 1 | 0 |
| 2025 | 0 | 0 |
| 2026 | 2 | 0 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Event-based debug, trace, and profile in device with data processing engine array7 Jul 2026US 12,675,420 B1Xilinx, Inc.
- Queue bypassing interrupt handling26 May 2026US 12,639,103 B2International Business Machines Corporation
- Enhanced low-priority arbitration23 Jul 2024US 12,045,182 B1Advanced Micro Devices, Inc.
- Enhanced low-priority arbitration13 Jun 2023US 11,675,718 B2Advanced Micro Devices, Inc.
- Event-based debug, trace, and profile in device with data processing engine array31 Jan 2023US 11,567,881 B1Xilinx, Inc.
- Queue bypassing interrupt handling16 Feb 2023US 2023/0052672 A1International Business Machines Corporation
- Enhanced Low-Priority Arbitration29 Sep 2022US 2022/0309013 A1Advanced Micro Devices, Inc.
- Adaptive Interrupt Coalescing16 Apr 2020US 2020/0117623 A1Petaio Inc.
- Circuitry system and method for processing interrupt priority23 Jan 2020US 2020/0026671 A1Realtek Semiconductor Corp.
- Managing efficient selection of a particular processor thread for handling an interrupt5 Dec 2019US 2019/0370198 A1International Business Machines Corporation
Most cited
By later US patents
- Method and apparatus for interrupt load balancing for powerPC processors36US 6,189,065 B1International Business Machines Corporation · 2001
- Method and system for assigning interrupts among multiple interrupt presentation controllers30US 6,430,643 B1International Business Machines Corporation · 2002
- Interrupt controller and method of operation of an interrupt controller8US 10,545,893 B1Arm Limited · 2020
- Managing efficient selection of a particular processor thread for handling an interrupt4US 10,423,550 B2International Business Machines Corporation · 2019
- Pessimistic interrupt affinity for devices4US 8,880,764 B2Red Hat Israel, Ltd. · 2014