Method and apparatus for interrupt load balancing for powerPC processors

A data processing system having a plurality of processors, comprising:

• logic within each processor for mapping special purpose registers wherein said mapped registers comprise, at least:
• a receive report register for holding a unique address for said processor;
• a signal pending buffer for holding a bit corresponding to an interrupt message address source;
• at least two masking registers for masking said interrupt message to determine said interrupt message priority;
• a next processor register for designating a next processor in line to receive an interrupt;
• means for directing an interrupt message to a first processor;
• an interrupt source register for storing the address of the highest priority queued said interrupt message;
• an offload selector for offloading said interrupt message to another processor if said first processor is busy servicing another interrupt signal;
• and
• means for offloading said interrupt message from each said busy processor to a processor, specified in said busy processor's next processor register, within said data processing system until said interrupt signal is accepted by one of said plurality of processors.

A computer-readable medium for servicing an interrupt message in a data processing system having a plurality of processors, comprising:

• instructions within said computer-readable medium for mapping special purpose registers in each of said plurality of processors wherein said mapping logic provides, at least:
• a receive port register for holding a unique address for said processor;
• a signal pending buffer for holding a bit location:
• at least two masking registers for said interrupt message;
• a next Processor register for designating a successive processor to receive an interrupt;
• instructions within said computer-readable medium for directing said interrupt message to a first processor;
• instructions within said computer-readable medium for masking said interrupt message to determine said interrupt message priority;
• instructions within said computer-readable medium for storing, in an interrupt source register, the address of the highest priority queued said interrupt message;
• instructions within said computer-readable medium for utilizing the contents of said signal pending buffer and said at least two masking registers for determining the interrupts that are queued in said first processor;
• instructions within said computer-readable medium for utilizing an offload selector for offloading a specific said interrupt message to a processor specified in said next processor register if said first processor is busy servicing another interrupt;
• and
• instructions within said computer-readable medium for offloading said interrupt message from each successive busy processor to a different processor within said data processing system until said interrupt message is accepted by one of said plurality of processors.