Enhanced Low-Priority Arbitration
AssigneeAdvanced Micro Devices, Inc.
InventorsEric Christopher Morton, Pravesh Gupta, Bryan P Broussard, Li Ou
Life of this patent
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Abstract
A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.
Claims20
A priority arbitration interrupt method, comprising:
- receiving an interrupt request from an input output hub (I/O hub) transmitted over an interconnect fabric;
- selecting a processor to interrupt from a cluster of processors based on the processor residing in a common domain with the I/O hub;
- and
- communicating an interrupt routine to the selected processor.
A programmable interrupt controller (PIC), comprising:
- an input configured to receive over an interconnect fabric an interrupt request from a device coupled to an input output hub (I/O hub);
- PIC logic configured to:
- in response to the interrupt request, select a processor to interrupt from a cluster of processors based on the processor residing in the same domain as the I/O hub and PIC;
- and
- communicate an interrupt service routine to the selected processor.
A computing system, comprising:
- an interconnect fabric;
- a core complex comprising a cluster of processors, the core complex coupled with the interconnect fabric;
- a programmable interrupt controller (PIC) coupled to PIC registers comprising arbitration priority registers (APR) and state registers, each APR and state register corresponding to a respective processor of the cluster of processors;
- and
- an input/output hub (I/O hub) coupled to one or more devices and the interconnect fabric, the I/O hub to send an interrupt request from the one or more devices to the PIC over the interconnect fabric, the PIC to select a processor to interrupt from the cluster of processors in the core complex based on the processor residing within a common domain with the I/O hub.
Dependencies are inferred from the claim text.