G06F 12/0851
Cache with interleaved addressing
Official title: {Cache with interleaved addressing}
G06F12/0851 (Cache with interleaved addressing) appears on 201 US grants and 188 published applications in this corpus.
Search patents in G06F- Granted patents
- 201
- Published applications
- 188
- Assignees
- 68
- Inventors
- 375
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 2 | 0 |
| 1984 | 2 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 3 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 5 | 0 |
| 1997 | 3 | 0 |
| 1998 | 5 | 0 |
| 1999 | 7 | 0 |
| 2000 | 4 | 0 |
| 2001 | 2 | 1 |
| 2002 | 4 | 1 |
| 2003 | 2 | 3 |
| 2004 | 0 | 5 |
| 2005 | 0 | 4 |
| 2006 | 5 | 8 |
| 2007 | 3 | 3 |
| 2008 | 3 | 4 |
| 2009 | 3 | 7 |
| 2010 | 4 | 4 |
| 2011 | 4 | 6 |
| 2012 | 6 | 1 |
| 2013 | 5 | 4 |
| 2014 | 4 | 6 |
| 2015 | 6 | 4 |
| 2016 | 6 | 6 |
| 2017 | 6 | 7 |
| 2018 | 5 | 8 |
| 2019 | 11 | 15 |
| 2020 | 8 | 17 |
| 2021 | 13 | 16 |
| 2022 | 16 | 17 |
| 2023 | 14 | 20 |
| 2024 | 14 | 7 |
| 2025 | 13 | 11 |
| 2026 | 5 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- In-flight incremental processing6 Oct 2026US 12,756,768 B2Intel Corporation
- Federated distribution of computation and operations using networked processing units15 Sep 2026US 12,739,313 B2Intel Corporation
- Techniques for storing data and tags in different memory arrays28 Apr 2026US 12,613,806 B2Rambus Inc.
- Hardware and software hybrid configuration of DRAM channel interleaving management7 Apr 2026US 12,596,641 B2QUALCOMM Incorporated
- Evenly distributing hierarchical binary hashes for strided workloads3 Mar 2026US 12,566,701 B2Intel Corporation
- Interleaving cache line data transfers and handling misses of speculatively fetched data30 Apr 2026US 2026/0119405 A1International Business Machines Corporation
- Framework for dram to physical address conversion9 Apr 2026US 2026/0099442 A1Microsoft Technology Licensing, LLC
- Shadow tag management for accelerator partitions19 Feb 2026US 2026/0050554 A1Advanced Micro Devices, Inc.
- Delayed snoop for multi-cache systems6 Nov 2025US 2025/0342081 A1
- Multicore shared cache operation engine23 Oct 2025US 2025/0328415 A1
Most cited
By later US patents
- System and method of increasing cache size251US 8,135,912 B2Hola Networks Ltd. · 2012
- Method for increasing cache size242US 8,719,505 B2Hola Networks Ltd. · 2014
- Method for increasing cache size238US 9,201,808 B2Hola Networks Ltd. · 2015
- Method for increasing cache size236US 9,990,295 B2Hola Newco Ltd. · 2018
- SDRAM data allocation system and method utilizing dual bank storage and retrieval129US 6,000,019 AHewlett-Packard Company · 1999