US 12,596,641 B2 · Hardware and software hybrid configuration of DRAM channel interleaving management

Abstract

Various embodiments include a memory controller and methods for implementing functions of the memory controller for hardware and software hybrid configuration of memory channel interleaving management. Embodiments may include a memory controller having a signaling mechanism configured to provide a configuration signal for indicating to the memory controller a layer of a memory channel interleaving hierarchy for software memory channel interleaving management, a processor configured to read the configuration signal and select the layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the configuration signal, and an integrated circuit configured to implement memory channel interleaving according to a layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management. In some embodiments, the layers for software or hardware memory channel interleaving management may include any of an intra-memory channel group, an inter-memory channel group, or an inter-die memory channel group layer.

Claims17

Dependent claims

A memory subsystem for a computing device, comprising:

at least one memory controller comprising:
at least one signaling mechanism configured to provide at least one configuration signal for indicating to the memory controller at least one layer of a memory channel interleaving hierarchy for software memory channel interleaving management;
at least one processor configured to:
read the at least one configuration signal;
select the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the at least one configuration signal;
and
load at least one memory map corresponding to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management, wherein the at least one memory map is configured to present a view of memory of the memory subsystem;
and
at least one integrated circuit configured to implement memory channel interleaving according to at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management concurrently with software memory channel interleaving management by the at least one processor.

6 more elements

A method for configuration of memory channel interleaving management implemented by a memory controller, comprising:

reading at least one configuration signal for indicating to the memory controller at least one layer of a memory channel interleaving hierarchy for software memory channel interleaving management;
selecting the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the at least one configuration signal;
implementing, by at least one integrated circuit, memory channel interleaving according to at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management concurrently with software memory channel interleaving management by the memory controller;
and
loading at least one memory map corresponding to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management, wherein the at least one memory map is configured to present a view of memory of the memory subsystem.

2 more elements

A computing device, comprising:

means for reading at least one configuration signal for indicating at least one layer of a memory channel interleaving hierarchy for software memory channel interleaving management;
means for selecting the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the at least one configuration signal;
means for implementing memory channel interleaving according to at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management concurrently with means for implementing software memory channel interleaving management;
and
means for loading at least one memory map corresponding to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management, wherein the at least one memory map is configured to present a view of memory of the memory subsystem.

2 more elements

Dependencies are inferred from the claim text.

Hardware and software hybrid configuration of DRAM channel interleaving management

Life of this patent

Hardware and software hybrid configuration of DRAM channel interleaving management

Life of this patent

Abstract

Claims17