Evenly distributing hierarchical binary hashes for strided workloads
AssigneeIntel Corporation
InventorWilliam Zorn
Life of this patent
Estimating the term…
Abstract
Described herein is a computer memory system comprising a plurality of memory banks or other memory structures and circuitry configured to implement a hash function that produces output values that evenly distribute strided memory accesses across the plurality of memory structures. The memory banks can be cache memory banks that may include a plurality of cache lines, cache sets, or cache ways. The memory banks can also be DRAM memory banks accessed through different memory channels. The hash function facilitates the even distribution across memory structures in the face of a plurality of different strided memory access patterns.
Claims20
A computer memory system comprising:
- a plurality of memory banks;
- and
- circuitry configured to implement a hash function configured to produce output values that evenly distribute strided memory accesses across the plurality of memory banks, wherein the hash function is representable by a binary matrix, the circuitry is configured to evenly distribute strided memory accesses according to a plurality of strided memory access patterns, the circuitry is configured to perform a modulo two binary matrix-vector product based on the binary matrix of the hash function and a binary input vector to generate a binary output vector, and the binary output vector is to select an element of the computer memory system.
A method comprising:
- receiving a plurality of memory access commands at controller circuitry of a memory device, the plurality of memory access commands having a strided access pattern;
- generating a first plurality of binary vectors based on addresses associated with the plurality of memory access commands;
- hashing the first plurality of binary vectors via circuitry configured to implement a hierarchical hash function to generate a second plurality of binary vectors;
- and
- distributing memory accesses for the plurality of memory access commands over a plurality of hierarchical levels of the memory device based on the second plurality of binary vectors, wherein the second plurality of binary vectors causes an even distribution of memory accesses in response to the strided access pattern of the plurality of memory access commands.
A graphics processor comprising:
- a memory device including a plurality of memory banks;
- a memory controller coupled with the memory device, the memory controller including circuitry configured to:
- receive a plurality of memory access commands at controller circuitry of a memory device, the plurality of memory access commands having a strided access pattern;
- and
- distribute memory accesses for the plurality of memory access commands evenly over a plurality of hierarchical levels of the memory device in response to the strided access pattern of the plurality of memory access commands, the plurality of hierarchical levels including the plurality of memory banks and a plurality of memory channels associated with the plurality of memory banks.
Dependencies are inferred from the claim text.