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US 2026/0050554 A1Published application
Shadow tag management for accelerator partitions
AssigneeAdvanced Micro Devices, Inc.
InventorsAmit P. Apte, Bryan P. Broussard, Vydhyanathan Kalyanasundharam, Ganesh Balakrishnan
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Abstract
The disclosed computer-implemented method includes interleaving a plurality of caches corresponding to a plurality of chiplets, identifying a source chiplet ID of a memory request of a new address for the interleaved caches, and storing, using an indexing scheme that incorporates the source chiplet ID, a shadow tag for a cache of the interleaved caches corresponding to the memory request. Various other methods, systems, and computer-readable media are also disclosed.
Claims21
-20. (canceled)
A device comprising:
- a plurality of chiplets, each chiplet having a cache;
- and
- a controller configured to:
- combine the caches corresponding to the plurality of chiplets into a combined cache;
- identify an address of the combined cache to be used with a memory request from one of the plurality of chiplets having a first chiplet ID;
- and
- track a state of one of the caches of the combined cache corresponding to the address associated with the memory request.
4 more elements
A system comprising:
- a plurality of chiplets, each chiplet having a cache;
- and
- a controller configured to:
- combine one or more of the plurality of chiplets and combine the corresponding caches into a larger cache;
- identify an address of the larger cache to be used with a memory request from one of the plurality of chiplets having a first chiplet ID;
- and
- track, using an indexing scheme that repurposes one or more address bits to incorporate the first chiplet ID, a state of one of the caches of the larger cache corresponding to the address associated with the memory request.
4 more elements
A method comprising:
- combining one or more of a plurality of chiplets, each chiplet having a cache, and combining the corresponding caches into a larger cache;
- identifying an address of the larger cache to be used with a memory request from one of the plurality of chiplets having a first chiplet ID;
- and
- storing, using an indexing scheme that incorporates the first chiplet ID, a shadow tag for one of the caches of the larger cache corresponding to the memory request, wherein the shadow tag indicates the address associated with the memory request and a state for corresponding data in the one of the caches.
1 more element
Dependencies are inferred from the claim text.