G06F 11/104
Using arithmetic codes, i.e. codes which are preserved during operation
Official title: {using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check}
G06F11/104 (Using arithmetic codes, i.e. codes which are preserved during operation) appears on 44 US grants and 29 published applications in this corpus.
Search patents in G06F- Granted patents
- 44
- Published applications
- 29
- Assignees
- 32
- Inventors
- 86
- Latest grant
- 7 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 2 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 2 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 2 |
| 2006 | 0 | 1 |
| 2007 | 0 | 1 |
| 2008 | 2 | 0 |
| 2009 | 2 | 0 |
| 2010 | 1 | 2 |
| 2011 | 1 | 2 |
| 2012 | 2 | 0 |
| 2013 | 2 | 0 |
| 2014 | 1 | 2 |
| 2015 | 0 | 0 |
| 2016 | 2 | 2 |
| 2017 | 0 | 0 |
| 2018 | 1 | 3 |
| 2019 | 2 | 4 |
| 2020 | 3 | 2 |
| 2021 | 3 | 1 |
| 2022 | 2 | 2 |
| 2023 | 3 | 0 |
| 2024 | 0 | 2 |
| 2025 | 0 | 2 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Error correction in computation7 Jul 2026US 12,675,549 B2Groq, Inc.
- Edge graph mapping using analog information with dynamically updated weighting factors for a surface GKP code26 Dec 2023US 11,853,159 B1Amazon Technologies, Inc.
- Preparation of qunaught states for a surface GKP code using a three (or higher) level ancilla system9 May 2023US 11,645,570 B1Amazon Technologies, Inc.
- Fault-tolerant quantum error correction with a surface GKP code7 Mar 2023US 11,599,820 B1Amazon Technologies, Inc.
- Storage system and method for using subcodes and convolutional-based LDPC interleaved coding schemes with read threshold calibration support25 Oct 2022US 11,481,271 B2Western Digital Technologies, Inc.
- Decoders, decoding methods, memory systems, and memory controllers26 Feb 2026US 2026/0056836 A1Yangtze Memory Technologies Co., Ltd.
- Arithmetic circuit, memory system, and method of controlling nonvolatile memory11 Sep 2025US 2025/0284586 A1Kioxia Corporation
- Systems and methods for memory recovery using secondary memory13 Mar 2025US 2025/0086054 A1Samsung Electronics Co., Ltd.
- Mac operator related to correcting a computational error29 Feb 2024US 2024/0069868 A1SK hynix Inc.
- Fault-mitigating method and data processing circuit25 Jan 2024US 2024/0028452 A1Skymizer Taiwan Inc.
Most cited
By later US patents
- System, method and storage medium for providing segment level sparing93US 7,539,800 B2International Business Machines Corporation · 2009
- Shared memory for a fault-tolerant computer32US 3,950,729 A1976
- Binary to modulo M translation32US 3,980,874 ABurroughs Corporation · 1976
- Device and process for detecting errors in an integrated circuit comprising a parallel-serial port28US 6,173,423 B2Bull SAS · 2001
- Error recovery within processing stages of an integrated circuit27US 7,320,091 B2Arm Limited · 2008