Shared memory for a fault-tolerant computer

A system including a fault-tolerant computer having a split-cycle read/write memory wherein the words stored in said memory include address verification check bytes, said system further comprising:

• a processor means, sharing said memory, for processing information independent of said fault-tolerant computer;
• means independent of said computer for reading a word from said memory at a desired address;
• means utilizing the check byte of the word read from memory for determining that the desired memory location was addressed, and initiating a signal to said fault-tolerant computer indicative of an incorrectly addressed word whenever an erroneous memory location is determined;
• and
• means responsive to said check byte utilizing means for rewriting the word, including the check byte, back into the same memory location from which the word was read.

In a system including a fault-tolerant computer, means for determining when data words read from a memory are incorrectly encoded or incorrectly addressed, and means responsive to said determining means for replacing or otherwise repairing the faulty memory, the improvement therein, comprising:

• a read/write memory for the computer, said read/write memory being of the split-cycle access type;
• a processor means independent of said computer for sharing said memory with said computer at times when said computer does not have access to said memory;
• control logic means in said processor means for causing delivery of an address and a read command to said memory during the first part of the cycle for said memory;
• an address register means for receiving an address signal for a desired location in said memory;
• a data register means for receiving information read from said memory which information includes a check byte indicative of the address from which the information is being read;
• an address check byte register means for receiving from said memory, said byte of information indicative of the address location of said memory that was actually addressed;
• means in said process for verifying whether the correct address location was accessed;
• and
• means responsive to said address vertification means and controlled by said control logic generator for rewriting during the second part of the cycle for said memory at the stored address information stored in said data register in the event an address other than said desired address was accessed.