Intle Corporation
Santa Clara, CA, US· latest recorded location
Intle Corporation is named on 10 US grants and 4 published applications in this corpus. Its most frequent classification is H10W (Generic packages, interconnections, connectors or other constructional details of devices covered by).
- Granted patents
- 10
- Published applications
- 4
- Inventors
- 18
- Granted in 2026 so far
- 0
- Most recent grant
- 8 Oct 2002
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 4 | 1 |
| 2002 | 5 | 2 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 1 |
By publication year.
Technology areas
Share of 14 documents
- H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by4
- G06FComputing and data processing3
- H10DInorganic electric semiconductor devices2
- B81BMicrostructural devices or systems1
- B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural1
- G01RMeasuring electric variables1
- G11CStatic stores1
- H01RElectrically-conductive connections1
- H03KPulse technique1
- H03MCoding1
Recent patents
- Gate array architecture8 Oct 2002US 6,462,583 B2
- Test socket for an electronic assembly which reduces damage to the electronic assembly10 Sep 2002US 6,447,322 B1
- Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure10 Sep 2002US 6,448,177 B1
- Interactive instruction scheduling and block ordering3 Sep 2002US 6,446,258 B1
- Voltage tolerant high drive pull-up driver for an I/O buffer14 May 2002US 6,388,475 B1
- Mold material architecture for package device structures31 Oct 2019US 2019/0330051 A1
- Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure3 Oct 2002US 2002/0140104 A1
- Interactive instruction scheduling and block ordering21 Mar 2002US 2002/0035722 A1
- Gate array architecture29 Nov 2001US 2001/0045846 A1
Most cited
By later US patents
- Operating system bootstrap security mechanism134US 6,263,431 B12001
- Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure33US 6,448,177 B12002
- Interactive instruction scheduling and block ordering30US 6,446,258 B12002
- Voltage tolerant high drive pull-up driver for an I/O buffer16US 6,388,475 B12002
- Test socket for an electronic assembly which reduces damage to the electronic assembly16US 6,447,322 B12002