d-MATRIX CORPORATION
Santa Clara, CA, US· latest recorded location
d-MATRIX CORPORATION is named on 11 US grants and 22 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 11
- Published applications
- 22
- Inventors
- 20
- Granted in 2026 so far
- 2
- Most recent grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2023 | 1 | 3 |
| 2024 | 3 | 7 |
| 2025 | 5 | 9 |
| 2026 | 2 | 3 |
By publication year. 2026 runs to 8 Oct.
Technology areas
Share of 33 documents
- G06FComputing and data processing32
- G06NAI and machine learning20
- H03MCoding3
- H05KPrinted circuits2
- H04LDigital communication1
- H10BElectronic memory devices1
- H10DInorganic electric semiconductor devices1
- H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by1
Recent patents
- Digital switch between chiplet devices for handling transformer workloads29 Sep 2026US 12,748,715 B1
- Methods and systems for allreduce optimization on small tensors26 May 2026US 12,639,253 B1
- AI accelerator apparatus using full mesh connectivity chiplet devices for transformer workloads12 Aug 2025US 12,386,774 B2
- Server system with AI accelerator apparatuses using in-memory compute chiplet devices for transformer workloads8 Jul 2025US 12,353,985 B2
- Hardware and software co-designed system for efficient distributed control of execution on a compute accelerator13 May 2025US 12,299,484 B1
- Artificial intelligence integrated circuit system configured with stacked three-dimensional memory devices30 Jul 2026US 2026/0223734 A1
- Transparent communications within and among nodes using a bridging network interface device for ai accelerator system28 May 2026US 2026/0147726 A1
- Stacked apparatus using in-memory compute chiplet devices for inference-time compute acceleration26 Feb 2026US 2026/0056891 A1
- Ai accelerator apparatus using full mesh connectivity chiplet devices for transformer workloads6 Nov 2025US 2025/0342134 A1
- Apparatus using in-memory compute chiplet devices for inference-time compute acceleration30 Oct 2025US 2025/0335374 A1
Most cited
By later US patents