Aspec Technology, Inc.
Sunnyvale, CA, US· latest recorded location
Aspec Technology, Inc. is named on 8 US grants and 0 published applications in this corpus. Its most frequent classification is H10D (Inorganic electric semiconductor devices).
- Granted patents
- 8
- Published applications
- 0
- Inventors
- 3
- Granted in 2026 so far
- 0
- Most recent grant
- 2 Oct 2001
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1995 | 2 | 0 |
| 1996 | 1 | 0 |
| 1997 | 2 | 0 |
| 1998 | 1 | 0 |
| 1999 | 0 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 0 |
By publication year.
Technology areas
Share of 8 documents
Recent patents
- Method and system for allowing an integrated circuit to be portably generated from one manufacturing process to another2 Oct 2001US 6,298,469 B1
- Method and system for porting an integrated circuit layout from a reference process to a target process11 Jul 2000US 6,088,518 A
- Low leakage output driver circuit which can be utilized in a multi-voltage source3 Mar 1998US 5,723,992 A
- Cell architecture for mixed signal applications23 Dec 1997US 5,701,021 A
- Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area3 Jun 1997US 5,635,737 A
No published applications.
Most cited
By later US patents
- Method and system for porting an integrated circuit layout from a reference process to a target process100US 6,088,518 A2000
- Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density47US 5,384,472 A1995
- Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density19US 5,493,135 A1996
- Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area18US 5,635,737 A1997
- Method and system for allowing an integrated circuit to be portably generated from one manufacturing process to another13US 6,298,469 B12001