US 5,635,737 AGranted

Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area

AssigneeAspec Technology, Inc.

InventorPatrick Yin

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Abstract

A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The architecture further includes a plurality of probe lines that are located within the architecture to facilitate testability of the outputs of the architecture.

Claims9

Dependent claims

An integrated circuit gate array structure comprising:

a semiconductor substrate in which are located a plurality of columns of semiconductor material of a first conductivity type and a plurality of columns of semiconductor material of a second conductivity type;
active areas formed within the columns for connecting conductive material, thereby forming active regions, each of the active regions including a contact point region, the contact point region including a plurality of contacts for electrical connection thereto;
the contact point region further including an extension portion that allows connection outside the active region without affecting any other connections to the structure;
a testability area comprising a plurality of probe lines located between the active regions, each of the probe lines including a pad member for facilitating connection to the active regions;
and
a plurality of tap regions formed outside the columns, each of the plurality of tap regions being associated with one pair of the columns, the tap regions being doped with an opposite conductivity with respect to the conductivity of their respective columns thereby allowing current and voltage characteristics of the columns to be controlled.

3 more elements

An integrated circuit gate array structure comprising:

a semiconductor substrate in which are located a plurality of columns of semiconductor material of a first conductivity type and a plurality of columns of semiconductor material of a second conductivity type;
the substrate having one of the first and second plurality of columns adjacent to each other and mirroring the next pair of columns such that the conductivity of the first column of the next pair of columns is the same as the last column of the first pair of columns;
active areas formed within the columns for connecting conductive material, thereby forming active regions, each of the active regions including a contact point region, the contact point region including an extension portion that allows connection outside the active region without affecting any other connections to the structure;
a testability area comprising a plurality of probe lines located between the active regions, each of the probe lines including a pad member for facilitating connection to the active regions;
and
a plurality of tap regions formed outside the columns, each of the plurality of tap regions being associated with one pair of the columns, the plurality of tap regions having the opposite conductivity with respect to the conductivity of the columns to which they are adjacent and allowing connection of conductive material, the tap regions being doped with an opposite conductivity with respect to the conductivity of their respective columns thereby allowing current and voltage characteristics of the columns to be controlled;
wherein the active areas and the tap regions adjacent to one of the columns are placed so as to form a plurality of adjacent cells, each cell comprising a first active area with an associated tap region located adjacent thereto and wherein pairs of columns are situated to allow common conductivity columns to share tap regions.

4 more elements

An integrated circuit gate array structure comprising:

a semiconductor substrate in which are located a plurality of columns of p-channel semiconductor material, the substrate having one of the plurality of p-channel columns adjacent to an n-channel column to form a first column pair, the substrate further having a next pair of columns positioned such that the next pair of columns mirror the first column pair such that the conductivity of the first column of the next pair of columns is the same as the last column of the first column pair;
active areas formed within the columns for connecting conductive material, thereby forming active regions, each of the active regions including a contact point region, the contact point region including an extension portion that allows connection outside the active region without affecting any other connections to the structure;
a testability area comprising a plurality of probe lines located between the active regions, each of the probe lines including a pad member for facilitating connection to the active regions;
and
a plurality of tap regions formed outside the column pairs, each of the plurality of tap regions being associated with one column pair, each of the tap regions having the opposite conductivity with respect to the conductivity of the columns to which they are adjacent thereby allowing connection of conductive material, and further being heavily doped thereby allowing current and voltage characteristics of the columns to be controlled,
wherein the active areas and the tap regions adjacent to one of the columns are placed so as to form a plurality of adjacent cells, each cell comprising a first active area with an associated tap region located adjacent thereto and a second active area and an associated tap region adjacent thereto and wherein pairs of columns are situated to allow common conductivity columns to share tap regions.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/574,496Filed 19 Dec 1995 · continuation
Priority: 23 Sep 1994
Granted: 3 Jun 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 84/907
Comprising field effect technology: cMOS gate arrays
Y10S 257/909
Active solid-state devices, e.g. transistors, solid-state diodes: macrocell arrays, e.g. gate arrays with variable size or configuration of cells
H10D
Inorganic electric semiconductor devices
Y10S
Technical subjects covered by former uspc cross-reference art collections [xracs] and digests