H04L 7/0095
Arrangements for synchronising receiver with transmitter: with mechanical means
Official title: {with mechanical means}
H04L7/0095 (Arrangements for synchronising receiver with transmitter: with mechanical means) appears on 3 US grants and 3 published applications in this corpus.
Search patents in H04L- Granted patents
- 3
- Published applications
- 3
- Assignees
- 4
- Inventors
- 20
- Latest grant
- 9 May 2023
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 1 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 1 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 1 | 1 |
| 2024 | 0 | 0 |
| 2025 | 0 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes9 May 2023US 11,646,861 B2International Business Machines Corporation
- Systems and methods for providing data channels at a die-to-die interface26 Jan 2016US 9,245,870 B1QUALCOMM Incorporated
- Phase synchronizing circuit10 May 1977US 4,023,080 AFuji Xerox Co., Ltd.
- Time synchronization system8 May 2025US 2025/0150251 A1Seiko Epson Corporation
- Low-latency, high-availability and high-speed serdes interface having multiple synchronization modes30 Mar 2023US 2023/0098514 A1International Business Machines Corporation
- Labeling Asymmetric Cables For Improved Network Clock Synchronization1 May 2008US 2008/0103713 A1
Most cited
By later US patents
- Systems and methods for providing data channels at a die-to-die interface5US 9,245,870 B1QUALCOMM Incorporated · 2016
- Phase synchronizing circuit2US 4,023,080 AFuji Xerox Co., Ltd. · 1977
- Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes1US 11,646,861 B2International Business Machines Corporation · 2023