H03M 13/395
Using a collapsed trellis
Official title: {using a collapsed trellis, e.g. M-step algorithm, radix-n architectures with n>2}
H03M13/395 (Using a collapsed trellis) appears on 72 US grants and 75 published applications in this corpus.
Search patents in H03M- Granted patents
- 72
- Published applications
- 75
- Assignees
- 44
- Inventors
- 157
- Latest grant
- 2 Sep 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 2 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 2 |
| 2003 | 1 | 2 |
| 2004 | 1 | 10 |
| 2005 | 0 | 6 |
| 2006 | 5 | 4 |
| 2007 | 6 | 10 |
| 2008 | 5 | 2 |
| 2009 | 4 | 8 |
| 2010 | 2 | 5 |
| 2011 | 9 | 3 |
| 2012 | 6 | 7 |
| 2013 | 8 | 4 |
| 2014 | 6 | 4 |
| 2015 | 3 | 2 |
| 2016 | 4 | 2 |
| 2017 | 1 | 1 |
| 2018 | 2 | 0 |
| 2019 | 0 | 1 |
| 2020 | 1 | 1 |
| 2021 | 1 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 0 |
| 2024 | 0 | 1 |
| 2025 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Decoding of series-concatenated turbo codes2 Sep 2025US 12,407,365 B2Safran Data Systems
- Method of Viterbi algorithm and receiving device31 Aug 2021US 11,108,415 B2ALi Corporation
- Early-termination of decoding convolutional codes9 Jun 2020US 10,680,749 B2Intel Corporation
- High speed turbo decoder25 Sep 2018US 10,084,486 B1Intel Corporation
- Electronic system with Viterbi decoder mechanism and method of operation thereof11 Sep 2018US 10,075,195 B2Samsung Electronics Co., Ltd.
- Decoding of series-concatenated turbo codes18 Jul 2024US 2024/0243756 A1Safran Data Systems
- Method of viterbi algorithm and receiving device27 Aug 2020US 2020/0274557 A1ALi Corporation
- Early-termination of decoding convolutional codes3 Jan 2019US 2019/0007068 A1Intel Corporation
- Decoding path selection device and method12 Oct 2017US 2017/0294924 A1Yuan Ze University
- Turbo decoders with extrinsic addressing and associated methods26 May 2016US 2016/0149668 A1Freescale Semiconductor, Inc.
Most cited
By later US patents
- Method and apparatus for generating branch metrics and branch indices for convolutional code Viterbi decoders67US 5,970,104 ACadence Design Systems, Inc. · 1999
- Method and apparatus for delayed recursion decoder66US 7,206,363 B2Intersymbol Communications, Inc. · 2007
- Error correction apparatus using a Viterbi decoder43US 4,606,027 ANEC Corporation · 1986
- Viterbi decoder with path metric comparisons for increased decoding rate and with normalization timing calculation41US 5,418,795 ASony Corporation · 1995
- Traceback stage for a viterbi decoder20US 5,987,637 ADiscovision Associates · 1999