Viterbi decoder with path metric comparisons for increased decoding rate and with normalization timing calculation
AssigneeSony Corporation
InventorsEisaburo Itakura, Yuichi Kojima
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AssigneeSony Corporation
InventorsEisaburo Itakura, Yuichi Kojima
Estimating the term…
A Viterbi decoding apparatus includes a brand metric calculation circuit for calculating a branch metric for a plurality of time slots at one time by an add-compare-select-state-metric (ACS-SM) calculation circuit for performing add-compare-select (ACS) calculation an add-compare-select-state-metric calculation circuit according to a branch metric for a plurality of time slots obtained by the branch metric calculation circuit and a state metric in the preceding stage at intervals of a plurality of time slots, and a maximum likelihood sequence decision circuit for decoding input data according to the content of the path obtained through the ACS calculation, wherein on the outside of a loop composed of the ACS-SM normalization circuit and a state metric storage circuit, there is provided a normalization command circuit, whereby a decision as to the necessity for normalization, a setting of the timing of normalization, and the like are performed, and, when it is decided that normalization is necessary, the state metric normalized through a bit shifting process in the ACS-SM normalization circuit is selected before at least any one of the state metrics overflows and the selected state metric is output as a new state metric.
A Viterbi decoding apparatus for decoding input data, comprising:
A viterbi decoding apparatus for decoding input data comprising:
Dependencies are inferred from the claim text.