Turbo decoders with extrinsic addressing and associated methods

A method of turbo decoding, the method comprising:

• (a) concurrently performing parallel turbo decoding operations on a received signal, wherein the received signal was encoded within rows and columns of an interleaving matrix where interleaved values stayed in a same re-ordered row during interleaving;
• (b) storing extrinsic values in extrinsic addressable memories used by the turbo decoding of said step (a);
• (c) read accessing the extrinsic addressable memories using extrinsic addresses for accessing the extrinsic addressable memories;
• (d) write accessing the extrinsic addressable memories using the extrinsic addresses for accessing the extrinsic addressable memories;
• and
• (e) deinterleaving to access the extrinsic addressable memories by arranging storage of the extrinsic values by the same rows of the same interleaving matrix that was used to encode the received signal, each of the rows corresponding to one of the concurrent turbo decoding operations of said step (a).

A turbo decoder comprising:

• a plurality of turbo decoder engines configured to concurrently decode a received signal encoded within rows and columns of an interleaving matrix where interleaved values stayed in a same re-ordered row during interleaving;
• a plurality of extrinsic addressable memories operatively coupled to the turbo decoder engines and configured to store extrinsic values used by the turbo decoder engines for the decoding;
• an extrinsic reader operatively coupled between the extrinsic addressable memories and the turbo decoder engines and configured to read from the extrinsic addressable memories using extrinsic addresses for accessing the extrinsic addressable memories;
• an extrinsic writer operatively coupled between the extrinsic addressable memories and the turbo decoder engines and configured to write to the extrinsic addressable memories using the extrinsic addresses for accessing the extrinsic addressable memories;
• and
• an address generator operatively coupled to the extrinsic reader and configured to access the extrinsic addressable memories by the same rows of the same interleaving matrix, which same rows were previously used to encode the received signal, and wherein the address generator is additionally configured to skip read of extrinsic values corresponding to dummy entries in the interleaving matrix.