H03M 13/1162
Array based ldpc codes
Official title: {Array based LDPC codes, e.g. array codes}
H03M13/1162 (Array based ldpc codes) appears on 63 US grants and 59 published applications in this corpus.
Search patents in H03M- Granted patents
- 63
- Published applications
- 59
- Assignees
- 44
- Inventors
- 127
- Latest grant
- 29 Jul 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 1 |
| 2004 | 0 | 0 |
| 2005 | 1 | 1 |
| 2006 | 0 | 1 |
| 2007 | 1 | 5 |
| 2008 | 2 | 2 |
| 2009 | 1 | 1 |
| 2010 | 3 | 2 |
| 2011 | 2 | 2 |
| 2012 | 4 | 5 |
| 2013 | 1 | 4 |
| 2014 | 9 | 4 |
| 2015 | 4 | 3 |
| 2016 | 6 | 4 |
| 2017 | 0 | 2 |
| 2018 | 2 | 3 |
| 2019 | 6 | 7 |
| 2020 | 5 | 3 |
| 2021 | 3 | 1 |
| 2022 | 3 | 3 |
| 2023 | 4 | 3 |
| 2024 | 2 | 1 |
| 2025 | 2 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same29 Jul 2025US 12,375,106 B2Electronics and Telecommunications Research Institute
- Optimizations of memory-utilization and PCM processing schedules for an LDPC decoder6 May 2025US 12,294,386 B2Tannera Technologies Doo
- Data processing device and data processing method22 Oct 2024US 12,126,359 B2Saturn Licensing LLC
- Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same23 Jul 2024US 12,047,095 B2Electronics and Telecommunications Research Institute
- Method, system, device and storage medium for constructing base matrix of PBRL LDPC code19 Dec 2023US 11,848,684 B2Chongqing University
- Optimizations of memory-utilization and pcm processing schedules for an ldpc decoder27 Feb 2025US 2025/0070797 A1Tannera Technologies Doo
- Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same26 Sep 2024US 2024/0322842 A1Electronics and Telecommunications Research Institute
- Data processing device and data processing method21 Dec 2023US 2023/0412193 A1Saturn Licensing LLC
- Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same31 Aug 2023US 2023/0275600 A1Electronics and Telecommunications Research Institute
- Method, system, device and storage medium for constructing base matrix of pbrl ldpc code23 Mar 2023US 2023/0087247 A1Chongqing University
Most cited
By later US patents
- Method and apparatus for low density parity check encoding of data217US 6,895,547 B2International Business Machines Corporation · 2005
- Methods and means for simultaneously correcting several channels in error in a parallel multi channel data system using continuously modifiable syndromes and selective generation of internal channel pointers106US 4,205,324 AInternational Business Machines Corporation · 1980
- Apparatus and method for transmitting and receiving data in communication/broadcasting system51US 9,214,960 B2Samsung Electronics Co., Ltd. · 2015
- Apparatus and method for coding/decoding block low density parity check code in a mobile communication system49US 7,313,752 B2Samsung Electronics Co., Ltd. · 2007
- Apparatus and method for transmitting and receiving data in communication/broadcasting system28US 8,782,499 B2Samsung Electronics Co., Ltd. · 2014