Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same
AssigneeElectronics and Telecommunications Research Institute
InventorsSung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim
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Abstract
A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
Claims2
A signaling information transmission method, comprising:
- generating a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of bit groups, and by group-wise interleaving the bit groups using an order of group-wise interleaving;
- generating parity punctured parity bits by performing the parity puncturing using the parity bit string;
- performing quadrature phase shift keying (QPSK) modulation for generating a transmission signal by using an input signal corresponding to the parity punctured parity bits;
- and
- transmitting the transmission signal over a physical channel to a reception device,
- wherein the bit groups correspond to 36 bit groups each of which is composed of 360 bits, and the 36 bit groups indexed by 36 integer numbers from 9 to 44,
- wherein the LDPC codeword includes zero-padded variable length signaling information as information bits.
Dependencies are inferred from the claim text.