Optimizations of memory-utilization and pcm processing schedules for an ldpc decoder
AssigneeTannera Technologies Doo
InventorsVladimir Petrovic, Dragomir El Mezeni, Milos Markovic
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Abstract
The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.
Claims16
An apparatus implementing a decoder with a layered decoder structure and the decoder configured to decode a sequence of codewords encoded with a low-density parity-check (LDPC) code using an iterative hybrid decoding algorithm, wherein the iterative hybrid decoding algorithm is based on passing messages between variable nodes and check nodes to decode a current codeword of the sequence of codewords in layers, the layers corresponding to portions of a parity check matrix (PCM) describing the LDPC code, wherein the iterative hybrid decoding algorithm includes a plurality of updates of log-likelihood ratios (LLRs) of a current codeword in decoding the current codeword, the apparatus comprising:
- an LLR update unit implemented by processing elements and configured to calculate, in processing a current layer of said layers of the PCM, updated LLRs of the current codeword for those variable nodes for which the current layer of the PCM includes non-zero entries;
- and
- an LLR memory, which is divided into a first memory block and a second memory block,
- wherein the first memory block is to store the most recent updated LLRs of the current codeword, and
- the second memory block stores LLRs of the next codework and, as patch LLRs, the most recent updated LLRs associated with a subset of the variable nodes for which a PCM processing schedule yields that variable-to-check messages from said associated variable nodes calculated in processing the current layer are not based on the most recent LLRs;
- and
- wherein each of the first and second memory blocks comprises a first memory portion having a number of bits equal to the number of bits required to store the values of the LLRs of the current or next codeword, respectively, and a second portion having a number of bits that is smaller than that of the first portion to store said patch LLRs for the variable nodes prior to their update.
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(canceled)
An apparatus implementing a decoder with a layered decoder structure and the decoder configured to decode a sequence of codewords encoded with a low-density parity-check, LDPC, code using an iterative hybrid decoding algorithm, wherein the iterative hybrid decoding algorithm is based on passing messages between variable nodes and check nodes to decode a current codeword of the sequence of codewords in layers, the layers corresponding to portions of a parity check matrix, PCM, describing the LDPC code, wherein the iterative hybrid decoding algorithm includes a plurality of updates of log-likelihood ratios, LLRs, of a current codeword in decoding the current codeword, the apparatus comprising:
- an LLR update unit implemented by processing elements and configured to calculate, in processing a current layer of said layers of the PCM, updated LLRs of the current codeword for those variable nodes for which the current layer of the PCM includes non-zero entries;
- and
- an LLR memory, which is divided into a first memory block, a second memory block and a third memory block,
- wherein the first memory block is to store the most recent updated LLRs of the current codeword,
- the second memory block is to store the LLRs of the next codeword, and
- the third memory block stores, as patch LLRs, the most recent updated LLRs associated with a subset of the variable nodes for which a PCM processing schedule yields that variable-to-check messages from said associated variable nodes calculated in processing the current layer are not based on the most recent LLRs, and
- wherein the number of bits that can be stored in the first and second memory blocks, respectively, is the number of bits required to store LLRs of the largest codeword length to be decoded by the apparatus, and the number of bits that can be stored in the third memory block is smaller than the number of bits that can be stored in the first and second memory blocks, respectively.
Dependencies are inferred from the claim text.