H03D 1/22
Homodyne or synchrodyne circuits
Official title: Homodyne or synchrodyne circuits {(receiver circuits H04B1/30)}
H03D1/22 (Homodyne or synchrodyne circuits) appears on 463 US grants and 108 published applications in this corpus.
Search patents in H03D- Granted patents
- 463
- Published applications
- 108
- Assignees
- 207
- Inventors
- 619
- Latest grant
- 7 Apr 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 16 | 0 |
| 1977 | 15 | 0 |
| 1978 | 10 | 0 |
| 1979 | 25 | 0 |
| 1980 | 8 | 0 |
| 1981 | 12 | 0 |
| 1982 | 10 | 0 |
| 1983 | 12 | 0 |
| 1984 | 13 | 0 |
| 1985 | 12 | 0 |
| 1986 | 15 | 0 |
| 1987 | 13 | 0 |
| 1988 | 13 | 0 |
| 1989 | 20 | 0 |
| 1990 | 17 | 0 |
| 1991 | 7 | 0 |
| 1992 | 14 | 0 |
| 1993 | 10 | 0 |
| 1994 | 14 | 0 |
| 1995 | 8 | 0 |
| 1996 | 8 | 0 |
| 1997 | 19 | 0 |
| 1998 | 15 | 0 |
| 1999 | 10 | 0 |
| 2000 | 3 | 0 |
| 2001 | 7 | 1 |
| 2002 | 7 | 7 |
| 2003 | 12 | 7 |
| 2004 | 7 | 9 |
| 2005 | 7 | 2 |
| 2006 | 11 | 8 |
| 2007 | 4 | 4 |
| 2008 | 4 | 10 |
| 2009 | 8 | 4 |
| 2010 | 9 | 2 |
| 2011 | 5 | 4 |
| 2012 | 8 | 5 |
| 2013 | 8 | 7 |
| 2014 | 8 | 3 |
| 2015 | 4 | 3 |
| 2016 | 4 | 1 |
| 2017 | 1 | 4 |
| 2018 | 2 | 5 |
| 2019 | 6 | 5 |
| 2020 | 4 | 2 |
| 2021 | 3 | 3 |
| 2022 | 4 | 3 |
| 2023 | 2 | 3 |
| 2024 | 4 | 2 |
| 2025 | 3 | 3 |
| 2026 | 2 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- H03D 1/2245Using two quadrature channels172
- H03D 1/2209Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal100
- H03D 1/24For demodulation of signals wherein one sideband or the carrier has been79
- H03D 1/229Using at least a two emittor-coupled differential pair of transistors24
- H03D 1/2281Using a phase locked loop18
- H03D 1/2272Using fet's16
Recent patents
- Compact, low-power, high image rejection sideband separation receiver7 Apr 2026US 12,596,081 B2Arizona Board of Regents On Behalfof Arizona State University
- Quadrature signal processor using single analog-to-digital converter unit24 Mar 2026US 12,587,427 B2NXP B. V.
- Measurement method with synchronous subsampling30 Dec 2025US 12,509,032 B2Safran Electronics & Defense
- Electronic devices with adjustable received sample bit width28 Oct 2025US 12,456,999 B2Apple Inc.
- Method for calibrating an SSB receiver3 Jun 2025US 12,323,280 B2Kapsch TrafficCom AG
- Digital envelope detector circuit, corresponding system-on-chip and method of operation26 Mar 2026US 2026/0088762 A1STMicroelectronics International N. V.
- Multi-path radio frequency system using local oscillation signals with frequencies having non-integer multiple relationship that are generated from same reference oscillation signal and associated local oscillation signal generation method7 Aug 2025US 2025/0253829 A1Mediatek Inc.
- Quadrature signal processor using single analog-to-digital converter unit19 Jun 2025US 2025/0202757 A1NXP B. V.
- Receiver architecture demodulating 4n-qam directly in analog domain without analog-to-digital converter (adc)22 May 2025US 2025/0168051 A1The Regents of the University of California
- Electronic Devices with Adjustable Received Sample Bit Width21 Mar 2024US 2024/0097727 A1Apple Inc.
Most cited
By later US patents
- Digital radio frequency receiver350US 4,893,316 AMotorola, Inc. · 1990
- Phase and gain error control system for use in an I/Q direct conversion receiver160US 5,249,203 ARockwell International Corporation · 1993
- Universal platform for software defined radio148US 6,823,181 B1Sony Corporation · 2004
- Method and apparatus for compensation of imbalance in zero-if downconverters134US 5,263,196 AMotorola, Inc. · 1993
- I/Q quadraphase modulator circuit126US 5,574,755 APhilips Electronics North America Corporation · 1996