US 4,893,316 A · Digital radio frequency receiver

Abstract

A digital radio receiver is described. The digital receiver of the present invention contemplates a digital radio receiver which operates on a received analog signal which has been converted to a digital form after preselection at the output of the antenna. The digital receiver of the present invention comprises a preselector, a high-speed analog-to-digital (A/D) converter, a digitally implemented intermediate-frequency (IF) selectivity section having an output signal at substantially baseband frequencies, and digital signal processor (DSP) circuit performing demodulation and audio filtering. The radio architecture of the present invention is programmably adaptable to virtually every known modulation scheme and is particularly suitable for implementation on integrated circuits.

Claims162

Dependent claims

An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising:

means for generating a noise signal which does not have any substantial energy at said given frequency;
means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter;
clock means for generating periodic pulses at a first frequency coupled to said A/D converter causing the latter to make A/D conversions in response to said pulses;
and
the resultant signal produced by said summing means containing the signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter.

2 more elements

A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device, comprising, in combination:

clock means for providing a periodic clock signal;
digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase;
means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz;
and
first and second digital filtering means, each comprising:
a decomposed, internally multiplexed, filter section coupled to said digitized output signals;
sample rate reducing means coupled to said decomposed filter section;
a multiplierless digital filter section coupled to said sample rate reducing means;
whereby, said first and second digital filtering means operate to selectively band-limit the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals.

6 more elements

A digital zero-IF selectivity section for operating on a received input signal in a receiver, comprising, in combination;

clock means for providing at least a first and second periodic clock signal;
digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase;
means for digital quadrature mixing the input signal and said first and second digitized signals for providing first and second digitized output signals such that said first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz;
first and second digital filtering means, each of said first and second digital filtering means comprising at least one digital filtering section coupled to a sample rate reducing means, and each of said first and second digital filtering means being coupled to said clock means for providing first and second filtered digitized output signals;
multiplexing means coupled to said first and second digital filter means to provide a multiplex output signal;
third digital filtering means, coupled to said multiplex means, comprising at least one digital filtering section, coupled to said clock means, for providing a selected order filter and to provide a filtered multiplex signal;
demultiplexing means coupled to said clock means and said filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.

4 more elements

A digital zero-If selectivity section for operating on a recovered input signal in a receiver, comprising, in combination:

clock means for providing a periodic first clock signal;
means for dividing the frequency of said clock signal to provide a second clock signal;
digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase;
means for digital quadrature mixing the input signal and said first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz;
first and second digital filtering section means respectively coupled to receive said first and second digitized output signals and each of said first and second digital filtering section means being coupled to said clock means for providing first and second filtered digitized output signals;
first and second data sampling rate reducer means respectively coupled to said first and second filtered digitized output signals for providing first and second reduced rate data signals;
multiplexing means coupled to said first and second reduced rate data signals to provide a multiplex output signal;
third digital filtering section means coupled to said second clock signal and said multiplex output signal to provide a first filtered multiplex signal;
fourth digital filtering section means coupled to said second clock signal and said first filtered multiplex signal to provide a second filtered multiplex signal;
fifth digital filtering section means coupled to said second clock signal and said second filtered multiplex signal to provide a third filtered multiplex signal;
and
demultiplexing means coupled to said second clock signal and said third filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.

9 more elements

A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device comprising, in combination:

clock means for providing a first and second periodic clock signal, such that said second clock signal has a period approximately twice that of said first clock signal;
digital oscillator means, coupled to said first clock signal, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase;
means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz;
and
first and second digital filtering means, each comprising:
at least two digital filter sections cascaded together for achieving a selected order digital filter, at least the first section comprising:
demultiplexing means, coupled to said digitized output signals for demultiplexing same into at least two demultiplexed signals;
first filtering means, coupled to said second clock signal, for filtering said demultiplexed signals providing at least two filtered demultiplexed signals;
multiplexing means for multiplexing said filtered demultiplexed signals into a multiplexed signal which represents a selectively band-limited portion of said input signal;
and
second filtering means coupled to said first clock signal and said multiplexed signal for providing a combined and filtered multiplexed output signal;
sample rate reducing means, coupled at least between the first and second filter sections, for reducing the operating speed of subsequent filter sections, each of said subsequent filter sections comprising:
first binary summing means coupled to an input signal and a second binary delayed signal for providing a first binary sum signal;
first binary shifting means coupled to said first binary sum signal for providing a shifted first binary sum signal;
second binary summing means coupled to said shifted first sum signal and a first binary delayed signal for providing a second binary sum signal;
first binary storage means coupled to said second binary sum signal for providing said first binary delayed signal;
third binary summing means coupled to said first binary delayed signal and said second delayed binary signal for providing a third binary sum signal;
second binary shifting means coupled to said third binary sum signal for providing a shifted third binary sum signal;
fourth binary summing means coupled to said shifted third binary sum signal and said second binary delayed signal for providing a fourth binary sum signal;
second binary storage means coupled to said fourth binary sum signal for providing said second binary delayed signal comprising a filtered digitized output signal;
whereby, said first and second digital filtering means operate to selectively band-limit the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals.

18 more elements

Dependencies are inferred from the claim text.

Digital radio frequency receiver

Life of this patent

Digital radio frequency receiver

Life of this patent

Abstract

Claims162