Measurement method with synchronous subsampling
AssigneeSafran Electronics & Defense
InventorDidier Levavasseur
Life of this patent
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Abstract
An electronic circuit (12) connected to a variable-excitation sensor (24) and comprising: a digital envelope detector (20) arranged to acquire signal that is produced by the sensor in response to an excitation signal, the detector comprising: an analog-to-digital converter (22) arranged to sample the measurement signal in such a manner as to produce sample points during successive observation windows of duration T that comprise a number NS of sample points, the sample points being spaced apart by a sampling period TS, the sampling period TS and the duration T being such that: TS=NP·T0+(NT/NS)·T0 and T=NS·TS, where T0 is one excitation period of the excitation signal, where NP, NT, and NS are non-zero natural integers, and where NT is not a multiple of NS.
Claims15
An electronic circuit arranged to be connected to a variable-excitation sensor for measuring a parameter, the electronic circuit comprising:
- synthesizer components arranged to use the same clock signal to produce both an excitation frequency, a sampling frequency, and an excitation signal at the excitation frequency, the excitation signal being applied as input to the variable-excitation sensor;
- and
- a digital envelope detector receiving as input a measurement signal that is produced by the variable-excitation sensor in response to the excitation signal, the digital envelope detector comprising:
- an analog-to-digital converter arranged to sample the measurement signal at the sampling frequency in such a manner as to produce sample points during successive observation windows, each observation window having a duration T and comprising a number Ns of sample points, the sample points being spaced apart by a sampling period Ts, the sampling period Ts and the duration T being such that:
- TS=NP·T0+(NT/NS)·T0 and T=NS·TS,
- where T0 is one excitation period of the excitation signal, where NP, NT, and NS are non-zero natural integers, and where NT is not a multiple of NS;
- and
- at least one processor component arranged to implement a synchronous demodulator arranged to produce, for each observation window, an output signal value on the basis of which the parameter is estimated.
Dependencies are inferred from the claim text.