G06F 2212/7209
Validity control
Official title: Validity control, e.g. using flags, time stamps or sequence numbers
G06F2212/7209 (Validity control) appears on 759 US grants and 833 published applications in this corpus.
Search patents in G06F- Granted patents
- 759
- Published applications
- 833
- Assignees
- 175
- Inventors
- 1,244
- Latest grant
- 11 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1995 | 1 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 0 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 0 |
| 2002 | 1 | 1 |
| 2003 | 0 | 2 |
| 2004 | 2 | 3 |
| 2005 | 3 | 2 |
| 2006 | 3 | 5 |
| 2007 | 1 | 4 |
| 2008 | 2 | 6 |
| 2009 | 3 | 13 |
| 2010 | 5 | 30 |
| 2011 | 14 | 24 |
| 2012 | 18 | 38 |
| 2013 | 26 | 35 |
| 2014 | 30 | 35 |
| 2015 | 55 | 59 |
| 2016 | 48 | 58 |
| 2017 | 57 | 45 |
| 2018 | 31 | 30 |
| 2019 | 45 | 52 |
| 2020 | 52 | 72 |
| 2021 | 70 | 108 |
| 2022 | 96 | 78 |
| 2023 | 84 | 55 |
| 2024 | 58 | 37 |
| 2025 | 35 | 28 |
| 2026 | 15 | 13 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Methods of memory address verification and memory devices employing the same11 Aug 2026US 12,705,183 B2
- Programming-in-process flag for fuse elements16 Jun 2026US 12,656,948 B2Micron Technology, Inc.
- Silent cache line eviction26 May 2026US 12,639,228 B2Micron Technology, Inc.
- Memory system controlling nonvolatile memory5 May 2026US 12,619,357 B2Kioxia Corporation
- Validity mapping techniques31 Mar 2026US 12,591,518 B2Micron Technology, Inc.
- Memory system controlling nonvolatile memory20 Aug 2026US 2026/0244340 A1Kioxia Corporation
- Short stripe repair in memory systems20 Aug 2026US 2026/0244347 A1Micron Technology, Inc.
- Memory system and address verification method11 Jun 2026US 2026/0161549 A1Kioxia Corporation
- Data storage method and related apparatus7 May 2026US 2026/0126913 A1
- Complete and incomplete superblock generation7 May 2026US 2026/0126924 A1Micron Technology, Inc.
Most cited
By later US patents
- System and method for managing trim operations in a flash memory system using mapping tables and block status tables334US 9,323,667 B2Violin Memory, Inc. · 2016
- Remove-on-delete technologies for solid state drive optimization323US 9,207,876 B2Microsoft Technology Licensing, LLC · 2015
- Partial block data programming and reading operations in a non-volatile memory321US 6,763,424 B2SanDisk Corporation · 2004
- System and method for tolerating a failed page in a flash device241US 9,047,214 B1PMC-Sierra, Inc. · 2015
- Nonvolatile memory with cluster-erase flash capability and solid state file apparatus using the same237US 5,598,370 AInternational Business Machines Corporation · 1997