Methods of memory address verification and memory devices employing the same
OwnerAlberto Troiainventor
Life of this patent
Estimating the term…
Abstract
A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.
Claims20
An apparatus, comprising:
- a volatile memory device comprising a first array of volatile memory cells;
- a non-volatile memory device comprising a second array of non-volatile memory cells;
- and
- a controller coupled with the volatile memory device and the non-volatile memory device, and configured to cause the apparatus to:
- generate a first physical address of the first array of volatile memory cells based at least in part on a read command indicating a logical address of the first array of volatile memory cells;
- read, based at least in part on the first physical address, a location identifier from a second physical address of the second array of non-volatile memory cells, wherein the second physical address of the second array of non-volatile memory cells is a same as the first physical address of the first array of volatile memory cells;
- and
- verify that the first physical address was generated without one or more errors based at least in part on determining that the location identifier corresponds to the logical address.
An apparatus, comprising:
- a volatile memory device comprising a first array of volatile memory cells;
- a non-volatile memory device comprising a second array of non-volatile memory cells;
- and
- a controller coupled with the volatile memory device and the non-volatile memory device, and configured to cause the apparatus to:
- generate a first physical address of the first array of volatile memory cells based at least in part on a write command indicating a logical address of the first array of volatile memory cells;
- read, based at least in part on the first physical address, a location identifier from a second physical address of the second array of non-volatile memory cells, wherein the second physical address of the second array of non-volatile memory cells is a same as the first physical address of the first array of volatile memory cells;
- and
- verify that the first physical address was generated without one or more errors based at least in part on determining that the location identifier corresponds to the logical address.
A method, comprising:
- generating a first physical address of a first array of volatile memory cells based at least in part on a read command indicating a logical address of the first array of volatile memory cells;
- reading, based at least in part on the first physical address, a location identifier from a second physical address of a second array of non-volatile memory cells, wherein the second physical address of the second array of non-volatile memory cells is a same as the first physical address of the first array of volatile memory cells;
- and
- verifying that the first physical address was generated without one or more errors based at least in part on determining that the location identifier corresponds to the logical address.
Dependencies are inferred from the claim text.