Semiconductor device and method for fabricating the same

A manufacturing method of a semiconductor device, comprising:

• forming first and second buried gates within first and second recesses of a semiconductor substrate, respectively, the first and second buried gates each being provided entirely within the first and second recesses, respectively;
• forming first and second sealing nitride films over the first and second buried gates and at least within the first and second recesses, respectively;
• forming first and second capping oxide films over the first and second sealing nitride films and at least within the first and second recesses, respectively;
• forming first and second dummy gates over the first and second capping oxide films, respectively, the first and second dummy gates defining a landing plug contact area therebetween;
• forming an interlayer dielectric over the first and second dummy gates and the landing plug contact area;
• etching the interlayer dielectric using the first and second dummy gates as etch masks to form a landing plug contact hole that exposes a surface of the semiconductor substrate, the landing plug contact hole corresponding to the landing plug contact area defined by the first and second dummy gates;
• and
• forming a landing plug within the landing plug contact hole, the landing plug contacting a junction region of the semiconductor substrate.

A manufacturing method of a semiconductor device, comprising:

• forming a recess in a semiconductor substrate;
• coating a gate oxide film over a surface of the recess;
• providing a gate conductive layer within the recess to form a buried gate, the buried gate being provided entirely within the recess;
• forming a sealing nitride film over a surface of the gate conductive layer and at least within the recess;
• forming a capping oxide film over the sealing nitride film and at least within the recess;
• depositing a dummy gate material over the semiconductor substrate;
• etching the dummy gate material to form a dummy gate over the buried gate;
• forming an interlayer dielectric over the semiconductor substrate including the dummy gate;
• etching the interlayer dielectric using the dummy gate as an etch mask to form a landing plug contact hole exposing the surface of the semiconductor substrate;
• and
• providing a landing plug material within the landing plug contact hole to form a landing plug adjacent to the dummy gate.