Recessed access device for a memory

A memory device including a recessed access device, the recessed device comprising:

• a device recess in semiconductor material;
• isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess;
• a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric;
• a gate in the device recess;
• and
• a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess, one of the pair of source/drain regions extending deeper into the semiconductor material than the other of the source/drain regions.

A memory device including a recessed access device, the recessed device comprising:

• a device recess in semiconductor material;
• isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess;
• a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric;
• a gate in the device recess;
• and
• a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess, one of the pair of source/drain regions being of higher conductivity than the other of the source/drain regions.

A memory cell comprising:

• a recessed access device comprising:
• a device recess in semiconductor material;
• isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess;
• a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric;
• a gate in the device recess;
• and
• a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess;
• a word line electrically coupled to the gate;
• and
• a pair of isolation structures laterally over opposing sides of the word line, the isolation structures respectively having an elevationally innermost surface, each elevationally innermost surface of the isolation structures being against an elevationally outermost surface of that portion of conductive material of the gate that is within the device recess.

A memory cell comprising:

• a recessed access device comprising:
• a device recess in semiconductor material;
• isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess;
• a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric;
• a gate in the device recess;
• and
• a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess;
• a word line electrically coupled to the gate;
• and
• a pair of isolation structures laterally over opposing sides of the word line, the isolation structures respectively having an elevationally innermost surface, each elevationally innermost surface of the isolation structures being against an elevationally outermost surface of a respective one of the pair of source/drain regions.

A memory device including a recessed access device, the recessed device comprising:

• a device recess in semiconductor material;
• isolation oxide laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess;
• a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation oxide, the isolation oxide being laterally thicker than the gate dielectric;
• a gate in the device recess;
• and
• a pair of source/drain regions in the semiconductor material against the isolation oxide on opposing sides of the device recess.

A memory device including a recessed access device, the recessed device comprising:

• a device recess in semiconductor material;
• isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess;
• a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation dielectric, the isolation dielectric being laterally thicker than the gate dielectric, the isolation dielectric and the gate dielectric being of the same composition relative one another;
• a gate in the device recess;
• and
• a pair of source/drain regions in the semiconductor material against the isolation dielectric on opposing sides of the device recess.

A plurality of memory cells at least some of which comprise:

• a substrate comprising semiconductor material;
• and
• a recessed access device formed within the semiconductor material, the recessed access device comprising:
• a device recess in the semiconductor material;
• isolation oxide laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess;
• a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation oxide, the isolation oxide being laterally thicker than the gate dielectric;
• a gate in the device recess;
• and
• a pair of source/drain regions in the semiconductor material against the isolation oxide on opposing sides of the device recess.

A plurality of memory cells at least some of which comprise:

• a substrate comprising semiconductor material;
• and
• a recessed access device formed within the semiconductor material, the recessed access device comprising:
• a device recess in the semiconductor material;
• isolation dielectric laterally against semiconductor material sidewalls of an elevationally outermost portion of the device recess;
• a gate dielectric laterally against semiconductor material sidewalls of the device recess elevationally inward of the isolation oxide, the isolation dielectric oxide being laterally thicker than the gate dielectric, the isolation dielectric and the gate dielectric being of the same composition relative one another;
• a gate in the device recess;
• and
• a pair of source/drain regions in the semiconductor material against the isolation oxide on opposing sides of the device recess.