Transistor, memory cell array and method of manufacturing a transistor

An integrated circuit including a memory cell array comprising:

• a plurality of bit lines extending in a first direction;
• a plurality of memory cells, each of the memory cells comprising a storage element and an access transistor configured to electrically couple the storage element to one of the bit lines, wherein individual ones of the access transistors are formed in a semiconductor material and comprise:
• doped portions arranged adjacent a top surface of the semiconductor material and extending to a first depth, wherein the doped portions of each of the access transistors comprise a first source/drain region and a second source/drain region;
• a channel region formed between the first and second source/drain regions and comprising a fin-like portion including a ridge with a top side and two lateral sides in a cross-section perpendicular to a first direction defined by a line extending between the first and second source/drain regions;
• and
• a gate electrode surrounding the ridge at the top side and the two lateral sides;
• and
• a plurality of word lines configured to address the access transistors and extending in a second direction intersecting the first direction;
• wherein a top surface of each of the word lines is disposed at a depth between the top surface of the semiconductor material and the first depth.