US 5,710,735 AGranted

EEPROM and method for fabricating the same

AssigneeHyundai Electronics Industries Co., Ltd.

InventorsKi Soo Shin, Soo Han Choi

Life of this patent

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Abstract

An EEPROM including a selecting gate which overlaps with one side of a floating gate and a certain part of a source electrode and a control gate which overlaps with the other side of the floating gate and a certain part of a drain electrode, is improved in charge coupling ratio, showing an increase in program efficiency even at low outer voltages. Application of low outer voltages to the EEPROM brings about a decrease in both the breakdown voltage and the junction breakdown voltage of the gate oxide film of peripheral transistors, allowing a shallow junction and a thin gate oxide film process to be possible. A shallow junction can be effected by an ion-implanting process which results in formation of a source electrode and a drain electrode.

Claims4

Dependent claims

An EEPROM, comprising:

a gate oxide film and a floating gate stacked on a semiconductor substrate;
a first interlayer insulating film formed on all exposed surfaces of the floating gate and the semiconductor substrate;
a selecting gate overlapping with the first interlayer insulating film from an upper surface of the floating gate to a portion of the semiconductor substrate;
a drain electrode and a source electrode formed in the semiconductor substrate which overlap with a portion of the floating gate and a portion of the selecting gate, respectively;
a second interlayer insulating film formed on all exposed surfaces of the first interlayer insulating film and the selecting gate;
a contact hole formed in the second interlayer insulating film, exposing the selecting gate;
and
a control gate which is in touch with the selecting gate through the contact hole and shields a surface portion of the floating gate which is not overlapped by the selecting gate.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/764,245Filed 12 Dec 1996 · division
Priority: KR 94-1729718 Jul 1994
Granted: 20 Jan 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 30/6891
Floating-gate IGFETs: characterised by the shapes, relative sizes or dispositions of the floating gate electrode
H10B
Electronic memory devices
H10D
Inorganic electric semiconductor devices

Family

Serial503,246Parent of this division · filed 17 Jul 1995
US 5,614,429 AParent of this division
US 5,710,735 AThis patent

From the US filing history. Foreign family members aren’t listed.

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